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Formation of vertical devices by electroplating Grant 8,247,905 - Deligianni , et al. August 21, 2 | 2012-08-21 |
Method of forming vertical contacts in integrated circuits Grant 7,803,639 - Assefa , et al. September 28, 2 | 2010-09-28 |
Formation Of Vertical Devices By Electroplating App 20090294989 - Deligianni; Hariklia ;   et al. | 2009-12-03 |
Formation of vertical devices by electroplating Grant 7,608,538 - Deligianni , et al. October 27, 2 | 2009-10-27 |
Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit Grant 7,531,367 - Assefa , et al. May 12, 2 | 2009-05-12 |
Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit App 20080211055 - Assefa; Solomon ;   et al. | 2008-09-04 |
Formation Of Vertical Devices By Electroplating App 20080166874 - Deligianni; Hariklia ;   et al. | 2008-07-10 |
Method of Forming Vertical Contacts in Integrated Circuits App 20080164617 - Assefa; Solomon ;   et al. | 2008-07-10 |
Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit App 20070166840 - Assefa; Solomon ;   et al. | 2007-07-19 |
Magnetic switching device Grant 7,097,777 - Costrini , et al. August 29, 2 | 2006-08-29 |
Encapsulation of conductive lines of semiconductor devices Grant 7,087,438 - Kasko , et al. August 8, 2 | 2006-08-08 |
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Magnetic switching device App 20050207064 - Costrini, Gregory ;   et al. | 2005-09-22 |
Method for improved alignment of magnetic tunnel junction elements Grant 6,933,204 - Sarma , et al. August 23, 2 | 2005-08-23 |
Method For Improved Alignment Of Magnetic Tunnel Junction Elements App 20050079683 - Sarma, Chandrasekhar ;   et al. | 2005-04-14 |
Patterning metal stack layers of magnetic switching device, utilizing a bilayer metal hardmask App 20040084400 - Costrini, Gregory ;   et al. | 2004-05-06 |
Dual damascene flowable oxide insulation structure and metallic barrier Grant 6,727,589 - Greco , et al. April 27, 2 | 2004-04-27 |
Insulating Cap Layer And Conductive Cap Layer For Semiconductor Devices With Magnetic Material Layers App 20040021188 - Low, Kia-Seng ;   et al. | 2004-02-05 |
Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers Grant 6,680,500 - Low , et al. January 20, 2 | 2004-01-20 |
Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same Grant 6,577,011 - Buchwalter , et al. June 10, 2 | 2003-06-10 |
Post metalization chem-mech polishing dielectric etch Grant 6,551,924 - Dalton , et al. April 22, 2 | 2003-04-22 |
Plasma treatment to enhance inorganic dielectric adhesion to copper App 20010053591 - Buchwalter, Leena P. ;   et al. | 2001-12-20 |
Interim oxidation of silsesquioxane dielectric for dual damascene process App 20010036739 - Cook, Robert ;   et al. | 2001-11-01 |
Plasma treatment to enhance inorganic dielectric adhesion to copper Grant 6,261,951 - Buchwalter , et al. July 17, 2 | 2001-07-17 |
Dual damascene flowable oxide insulation structure and metallic barrier App 20010000115 - Greco, Stephen E. ;   et al. | 2001-04-05 |
Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same Grant 6,184,121 - Buchwalter , et al. February 6, 2 | 2001-02-06 |
Process for forming a circuit assembly Grant 5,633,034 - Carter , et al. May 27, 1 | 1997-05-27 |