| Patent | Date |
|---|
Master/slave power supply switch driver circuitry
Grant 8,558,524 - Carroll , et al. October 15, 2 | 2013-10-15 |
Switching power supply gate driver
Grant 8,476,939 - Candage , et al. July 2, 2 | 2013-07-02 |
Master/slave Power Supply Switch Driver Circuitry
App 20120091977 - Carroll; Robert T. ; et al. | 2012-04-19 |
Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics
Grant 7,443,250 - Seethamraju , et al. October 28, 2 | 2008-10-28 |
Technique for switching between input clocks in a phase-locked loop
Grant 7,405,628 - Hulfachor , et al. July 29, 2 | 2008-07-29 |
Programmable Phase-locked Loop Responsive To A Selected Bandwidth And A Selected Reference Clock Signal Frequency To Adjust Circuit Characteristics
App 20080079510 - Seethamraju; Srisai R. ; et al. | 2008-04-03 |
Technique For Switching Between Input Clocks In A Phase-locked Loop
App 20080079501 - Hulfachor; Ronald B. ; et al. | 2008-04-03 |
Tunable high-speed frequency divider
Grant 7,348,818 - Hulfachor , et al. March 25, 2 | 2008-03-25 |
Active power/ground ESD trigger
Grant 7,079,369 - Hulfachor , et al. July 18, 2 | 2006-07-18 |
Circuit to linearize gain of a voltage controlled oscillator over wide frequency range
Grant 7,030,669 - Hulfachor , et al. April 18, 2 | 2006-04-18 |
Circuitry to reduce PLL lock acquisition time
Grant 6,940,356 - McDonald, II , et al. September 6, 2 | 2005-09-06 |
Method and structure for BiCMOS isolated NMOS transistor
Grant 6,927,460 - Leibiger , et al. August 9, 2 | 2005-08-09 |
Capacitively coupled current boost circuitry for integrated voltage regulator
Grant 6,894,553 - Hulfachor , et al. May 17, 2 | 2005-05-17 |
Triggering of an ESD NMOS through the use of an N-type buried layer
Grant 6,855,964 - Hulfachor February 15, 2 | 2005-02-15 |
PLL for clock recovery with initialization sequence
Grant 6,794,945 - McDonald, II , et al. September 21, 2 | 2004-09-21 |
Circuit to linearize gain of a voltage controlled oscillator over wide frequency range
App 20040164815 - Hulfachor, Ronald B. ; et al. | 2004-08-26 |
Circuitry to reduce PLL lock acquisition time
App 20040160281 - McDonald, James J. II ; et al. | 2004-08-19 |
Capacitively coupled current boost circuitry for integrated voltage regulator
App 20040021503 - Hulfachor, Ronald B. ; et al. | 2004-02-05 |
PLL for clock recovery with initialization sequence
App 20030193374 - McDonald, James J. II ; et al. | 2003-10-16 |
Triggering of an ESD NMOS through the use of an N-type buried layer
App 20030085429 - Hulfachor, Ronald B. | 2003-05-08 |
Active power/ground ESD trigger
App 20030026054 - Hulfachor, Ronald B. ; et al. | 2003-02-06 |
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