Huisman; Leendert M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Huisman; Leendert M..The latest application filed is for "using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection".

Company Profile

0.22.18

Huisman; Leendert M. - South Burlington VT
Huisman, Leendert M. - So. Burlington VT
Huisman, Leendert M. - Burlington VT
Huisman; Leendert M. - Peekskill NY
Huisman; Leendert M. - Ossining NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Scan chain diagnostics using logic paths Grant 7,895,487 - Huisman , et al. February 22, 2	2011-02-22
Methods and apparatus for testing a scan chain to isolate defects Grant 7,752,514 - Huisman , et al. July 6, 2	2010-07-06
Learning based logic diagnosis Grant 7,558,999 - Adkisson , et al. July 7, 2	2009-07-07
Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection Grant 7,434,130 - Huisman , et al. October 7, 2	2008-10-07
Using Clock Gating Or Signal Gating To Partition A Device For Fault Isolation And Diagnostic Data Collection App 20080098268 - Huisman; Leendert M. ; et al.	2008-04-24
Methods And Apparatus For Testing A Scan Chain To Isolate Defects App 20080059857 - HUISMAN; LEENDERT M. ; et al.	2008-03-06
Methods and apparatus for testing a scan chain to isolate defects Grant 7,313,744 - Huisman , et al. December 25, 2	2007-12-25
Scan Chain Diagnostics Using Logic Paths App 20070168805 - Huisman; Leendert M. ; et al.	2007-07-19
Scan chain diagnostics using logic paths Grant 7,240,261 - Huisman , et al. July 3, 2	2007-07-03
Inspection methods and structures for visualizing and/or detecting specific chip structures Grant 7,230,335 - Cann , et al. June 12, 2	2007-06-12
Designing scan chains with specific parameter sensitivities to identify process defects Grant 7,194,706 - Adkisson , et al. March 20, 2	2007-03-20
Segmented scan chains with dynamic reconfigurations Grant 7,139,950 - Huisman , et al. November 21, 2	2006-11-21
Defect diagnosis for semiconductor integrated circuits Grant 7,089,514 - Adkisson , et al. August 8, 2	2006-08-08
Inspection Methods And Structures For Visualizing And/or Detecting Specific Chip Structures App 20060071208 - Cann; Jerome L. ; et al.	2006-04-06
Defect Diagnosis For Semiconductor Integrated Circuits App 20060036975 - Adkisson; James W. ; et al.	2006-02-16
Designing Scan Chains With Specific Parameter Sensitivities to Identify Process Defects App 20060026472 - Adkisson; James W. ; et al.	2006-02-02
Learning Based Logic Diagnosis App 20050273656 - Adkisson, James W. ; et al.	2005-12-08
Methodology for fixing Qcrit at design timing impact Grant 6,954,916 - Bernstein , et al. October 11, 2	2005-10-11
Methods And Apparatus For Defect Isolation App 20050193297 - Huisman, Leendert M. ; et al.	2005-09-01
Rapid fail analysis of embedded objects Grant 6,931,580 - Barcomb , et al. August 16, 2	2005-08-16
Segmented Scan Chains With Dynamic Reconfigurations App 20050166108 - Huisman, Leendert M. ; et al.	2005-07-28
Scan Chain Diagnostics Using Logic Paths App 20050138508 - Huisman, Leendert M. ; et al.	2005-06-23
Internal cache for on chip test data storage Grant 6,901,542 - Bartenstein , et al. May 31, 2	2005-05-31
Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection App 20050108599 - Huisman, Leendert M. ; et al.	2005-05-19
Method to detect systematic defects in VLSI manufacturing Grant 6,880,136 - Huisman , et al. April 12, 2	2005-04-12
Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection Grant 6,865,501 - Huisman , et al. March 8, 2	2005-03-08
METHODOLOGY FOR FIXING Qcrit AT DESIGN TIMING IMPACT App 20040267514 - Bernstein, Kerry ; et al.	2004-12-30
Rapid defect analysis by placement of tester fail data Grant 6,785,413 - Barcomb , et al. August 31, 2	2004-08-31
Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection App 20040093185 - Huisman, Leendert M. ; et al.	2004-05-13
Diagnosis of combinational logic circuit failures Grant 6,721,914 - Bartenstein , et al. April 13, 2	2004-04-13
Method to detect systematic defects in VLSI manufacturing App 20040009616 - Huisman, Leendert M. ; et al.	2004-01-15
Incremental fault dictionary Grant 6,675,323 - Bartenstein , et al. January 6, 2	2004-01-06
Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection Grant 6,671,644 - Huisman , et al. December 30, 2	2003-12-30
Incremental fault dictionary App 20030046608 - Bartenstein, Thomas W. ; et al.	2003-03-06
Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection App 20030036869 - Huisman, Leendert M. ; et al.	2003-02-20
Internal cache for on chip test data storage App 20030033566 - Bartenstein, Thomas W. ; et al.	2003-02-13
Diagnosis of RAMS using functional patterns Grant 6,519,725 - Huisman , et al. February 11, 2	2003-02-11
Diagnosis of combinational logic circuit failures App 20020147952 - Bartenstein, Thomas W. ; et al.	2002-10-10
Adjustable weighted random test pattern generator for logic circuits Grant 5,297,151 - Gruetzner , et al. March 22, 1	1994-03-22
Determination of testability of combined logic end memory by ignoring memory Grant 4,726,023 - Carter , et al. February 16, 1	1988-02-16

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.