Huang; Yaohuang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Huang; Yaohuang.The latest application filed is for "electronic device including electrically conductive vias having different cross-sectional areas and related methods".

Company Profile

0.12.12

Huang; Yaohuang - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuit module with multiple submodules Grant 9,171,823 - Gan , et al. October 27, 2	2015-10-27
Embedded wafer level package for 3D and package-on-package applications, and method of manufacture Grant 8,916,481 - Gan , et al. December 23, 2	2014-12-23
Electronic device including electrically conductive vias having different cross-sectional areas and related methods Grant 8,860,228 - Jin , et al. October 14, 2	2014-10-14
System in package manufacturing method using wafer-to-wafer bonding Grant 8,822,267 - Hwang , et al. September 2, 2	2014-09-02
Embedded wafer level package for 3D and package-on-package applications, and method of manufacture Grant 8,779,601 - Gan , et al. July 15, 2	2014-07-15
Through hole via filling using electroless plating Grant 8,766,422 - Gan , et al. July 1, 2	2014-07-01
Electronic Device Including Electrically Conductive Vias Having Different Cross-sectional Areas And Related Methods App 20140175649 - Jin; Yonggang ; et al.	2014-06-26
System In Package Manufacturing Method Using Wafer-to-wafer Bonding App 20140113410 - Hwang; How Yuan ; et al.	2014-04-24
Through hole via filling using electroless plating Grant 8,617,987 - Gan , et al. December 31, 2	2013-12-31
Circuit Module With Multiple Submodules App 20130170169 - GAN; KahWee ; et al.	2013-07-04
Embedded Wafer Level Package For 3d And Package-on-package Applications, And Method Of Manufacture App 20130105991 - Gan; Kah Wee ; et al.	2013-05-02
Embedded Wafer Level Package For 3d And Package-on-package Applications, And Method Of Manufacture App 20130105973 - Gan; Kah Wee ; et al.	2013-05-02
Method For Producing A Two-sided Fan-out Wafer Level Package With Electrically Conductive Interconnects, And A Corresponding Semiconductor Package App 20120282767 - Jin; Yonggang ; et al.	2012-11-08
Through Hole Via Filling Using Electroless Plating App 20120168944 - Gan; Kah Wee ; et al.	2012-07-05
Through Hole Via Filling Using Electroless Plating App 20120168942 - Gan; Kah Wee ; et al.	2012-07-05
Ball Grid Array Method And Structure App 20120161319 - Huang; Yaohuang ; et al.	2012-06-28

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