loadpatents
Patent applications and USPTO patent grants for Huang; Weng-Hsing.The latest application filed is for "[memory device and method for fabricating the same]".
Patent | Date |
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Memory device and method for fabricating the same Grant 6,777,285 - Huang , et al. August 17, 2 | 2004-08-17 |
[memory Device And Method For Fabricating The Same] App 20040110344 - Huang, Weng-Hsing ;   et al. | 2004-06-10 |
Memory device structure with composite buried and raised bit line Grant 6,710,381 - Huang , et al. March 23, 2 | 2004-03-23 |
Structure of a memory device and fabrication method thereof App 20040031983 - Huang, Weng-Hsing ;   et al. | 2004-02-19 |
Method for improving the reliability of flash memories Grant 6,673,720 - Huang , et al. January 6, 2 | 2004-01-06 |
STI method for semiconductor processes App 20030181048 - Huang, Weng-Hsing ;   et al. | 2003-09-25 |
Method of fabricating a flash memory cell App 20030181051 - Chang, Kent Kuohua ;   et al. | 2003-09-25 |
Method for reducing random bit failures of flash memories App 20030181007 - Huang, Weng-Hsing ;   et al. | 2003-09-25 |
Method for reducing particles and defects during flash memory fabrication App 20030181008 - Huang, Weng-Hsing ;   et al. | 2003-09-25 |
Method for improving reliability of STI App 20030181049 - Huang, Weng-Hsing ;   et al. | 2003-09-25 |
Memory device with low resistance buried bit lines Grant 6,624,460 - Huang , et al. September 23, 2 | 2003-09-23 |
Method for improving the reliability of flash memories App 20030160241 - Huang, Weng-Hsing ;   et al. | 2003-08-28 |
Method of forming a via of a dual damascene with low resistance App 20020123219 - Laverty, Jerald ;   et al. | 2002-09-05 |
Method of forming a three-dimensional polysilicon layer on a semiconductor wafer App 20020055226 - Liu, Chen-Chin ;   et al. | 2002-05-09 |
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