| Patent | Date |
|---|
Body-tied, strained-channel multi-gate device and methods
Grant 9,653,552 - Lin , et al. May 16, 2 | 2017-05-16 |
Body-Tied, Strained-Channel Multi-Gate Device and Methods
App 20160322463 - Lin; Hong-Nien ; et al. | 2016-11-03 |
Body-tied, strained-channel multi-gate device and methods of manufacturing same
Grant 9,406,800 - Lin , et al. August 2, 2 | 2016-08-02 |
Body-Tied, Strained-Channel Multi-Gate Device and Methods of Manufacturing Same
App 20160104800 - Lin; Hong-Nien ; et al. | 2016-04-14 |
Body-tied, strained-channel multi-gate device and methods of manufacturing same
Grant 9,214,554 - Lin , et al. December 15, 2 | 2015-12-15 |
Body-tied, strained-channel multi-gate device and methods of manufacturing same
Grant 8,946,811 - Lin , et al. February 3, 2 | 2015-02-03 |
Body-tied, strained-channel multi-gate device and methods of manufacturing same
App 20080006908 - Lin; Hong-Nien ; et al. | 2008-01-10 |
Single-electron transistor and fabrication method thereof
Grant 6,894,352 - Hu , et al. May 17, 2 | 2005-05-17 |
Single-electron transistor and fabrication method thereof
App 20040061173 - Hu, Shu-Fen ; et al. | 2004-04-01 |
Nonvolatile memory having a split gate
Grant 6,667,508 - Lin , et al. December 23, 2 | 2003-12-23 |
Nonvolatile memory and method of manufacturing the same
App 20020163032 - Lin, Horng-Chih ; et al. | 2002-11-07 |
Method of improving a dual gate CMOS transistor to resist the boron-penetrating effect
App 20020022329 - Chen, Chi-Chun ; et al. | 2002-02-21 |
Method of forming a gate oxide layer with an improved ability to resist the process damage
App 20020019085 - Chen, Chi-Chun ; et al. | 2002-02-14 |
Thin film transistor with sub-gates and schottky source/drain and a manufacturing method of the same
App 20020009833 - Lin, Horng-Chih ; et al. | 2002-01-24 |
Test structure for monitoring overetching of silicide during contact opening
Grant 6,087,189 - Huang July 11, 2 | 2000-07-11 |
Method for simultaneously forming local interconnect with silicided elevated source/drain MOSFET's
Grant 5,893,741 - Huang April 13, 1 | 1999-04-13 |
Method for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structure
Grant 5,827,768 - Lin , et al. October 27, 1 | 1998-10-27 |
Forming a MOS transistor with a recessed channel
Grant 5,814,544 - Huang September 29, 1 | 1998-09-29 |
Structure and method for manufacturing improved FETs having T-shaped gates
Grant 5,783,479 - Lin , et al. July 21, 1 | 1998-07-21 |
Method for making an integrated circuit structure
Grant 5,529,941 - Huang June 25, 1 | 1996-06-25 |
CMOS output buffer with enhanced ESD resistance
Grant 5,517,049 - Huang May 14, 1 | 1996-05-14 |
Semiconductor-on-insulator integrated circuit with selectively thinned channel region
Grant 5,418,391 - Huang May 23, 1 | 1995-05-23 |
Differential treatment to selectively avoid silicide formation on ESD I/O transistors in a salicide process
Grant 5,413,969 - Huang May 9, 1 | 1995-05-09 |
Asymmetric electro-static discharge transistors for increased electro-static discharge hardness
Grant 5,386,134 - Huang January 31, 1 | 1995-01-31 |
Method for selective salicidation of source/drain regions of a transistor
Grant 5,342,798 - Huang August 30, 1 | 1994-08-30 |
Thin film varactors
Grant 5,038,184 - Chiang , et al. August 6, 1 | 1991-08-06 |
Method of fabrication a thin film SOI CMOS device
Grant 4,988,638 - Huang , et al. January 29, 1 | 1991-01-29 |
Method for fabricating double implanted LDD transistor self-aligned with gate
Grant 4,963,504 - Huang October 16, 1 | 1990-10-16 |
Simultaneously deposited thin film CMOS TFTs and their method of fabrication
Grant 4,951,113 - Huang , et al. August 21, 1 | 1990-08-21 |
Double implanted LDD transistor self-aligned with gate
Grant 4,907,048 - Huang March 6, 1 | 1990-03-06 |
Formation of large grain polycrystalline films
Grant 4,904,611 - Chiang , et al. February 27, 1 | 1990-02-27 |
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