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Patent applications and USPTO patent grants for Huang; Rainer Yen-Chieh.The latest application filed is for "ferroelectric memory device, manufacturing method of the ferroelectric memory device and semiconductor chip".
Patent | Date |
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Carrier Barrier Layer For Tuning A Threshold Voltage Of A Ferroelectric Memory Device App 20220285519 - Huang; Rainer Yen-Chieh ;   et al. | 2022-09-08 |
Ferroelectric Memory Device, Manufacturing Method Of The Ferroelectric Memory Device And Semiconductor Chip App 20220285396 - Huang; Rainer, Yen-Chieh ;   et al. | 2022-09-08 |
Annealed Seed Layer To Improve Ferroelectric Properties Of Memory Layer App 20220271047 - Liao; Song-Fu ;   et al. | 2022-08-25 |
Stacked Ferroelectric Structure App 20220271046 - Huang; Rainer Yen-Chieh ;   et al. | 2022-08-25 |
Cocktail Layer Over Gate Dielectric Layer Of Fet Feram App 20220254793 - Huang; Rainer Yen-Chieh ;   et al. | 2022-08-11 |
Capping Layer Over Fet Feram To Increase Charge Mobility App 20220254794 - Huang; Rainer Yen-Chieh ;   et al. | 2022-08-11 |
Memory Device And Method For Fabricating The Same App 20220139935 - Huang; Rainer Yen-Chieh ;   et al. | 2022-05-05 |
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