| Patent | Date |
|---|
Semiconductor Package and Method of Manufacture
App 20220310480 - Bao; Xinyu ; et al. | 2022-09-29 |
Back-end-of-line Devices
App 20220293749 - Chen; Yu-Hsiang ; et al. | 2022-09-15 |
Integrated circuit having a high cell density
Grant 11,437,319 - Chen , et al. September 6, 2 | 2022-09-06 |
Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit
Grant 11,437,708 - Huang , et al. September 6, 2 | 2022-09-06 |
Display Method And Display Device Using The Same
App 20220270535 - CHIANG; HSIN-TSO ; et al. | 2022-08-25 |
E-fuse enhancement by underlayer layout design
Grant 11,410,926 - Fu , et al. August 9, 2 | 2022-08-09 |
Display method and display device using the same
Grant 11,410,592 - Chiang , et al. August 9, 2 | 2022-08-09 |
Semiconductor device and method of manufacture
Grant 11,410,929 - Chang , et al. August 9, 2 | 2022-08-09 |
Package Structure And Method For Forming The Same
App 20220246509 - CHIEN; CHIN-HER ; et al. | 2022-08-04 |
Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same
Grant 11,397,842 - Chang , et al. July 26, 2 | 2022-07-26 |
Package structure and method for forming the same
Grant 11,387,177 - Chien , et al. July 12, 2 | 2022-07-12 |
Interposer with capacitors
Grant 11,367,695 - Chang , et al. June 21, 2 | 2022-06-21 |
Robot Using Liquid Crystal Display Panel
App 20220163839 - Tsai; Hsiu Min ; et al. | 2022-05-26 |
Semiconductor Device Having Fuse Array And Method Of Making The Same
App 20220157718 - CHANG; Meng-Sheng ; et al. | 2022-05-19 |
Package Structure, Semiconductor Device And Manufacturing Method Thereof
App 20220149020 - CHANG; Fong-yuan ; et al. | 2022-05-12 |
Layout Design Methodology For Stacked Devices
App 20220130818 - Chang; Fong-Yuan ; et al. | 2022-04-28 |
Cell structures and semiconductor devices having same
Grant 11,281,836 - Chang , et al. March 22, 2 | 2022-03-22 |
Standard Cells And Variations Thereof Within A Standard Cell Library
App 20220067266 - CHEN; Sheng-Hsiung ; et al. | 2022-03-03 |
Semiconductor device having fuse array and method of making the same
Grant 11,257,757 - Chang , et al. February 22, 2 | 2022-02-22 |
Heat Dissipation In Semiconductor Packages And Methods Of Forming Same
App 20220028842 - Chang; Fong-yuan ; et al. | 2022-01-27 |
Layout design methodology for stacked devices
Grant 11,222,884 - Chang , et al. January 11, 2 | 2022-01-11 |
Through silicon via optimization for three-dimensional integrated circuits
Grant 11,211,333 - Chang , et al. December 28, 2 | 2021-12-28 |
Heat Dissipation Structures
App 20210375717 - HUANG; Po-Hsiang ; et al. | 2021-12-02 |
Standard cells and variations thereof within a standard cell library
Grant 11,182,533 - Chen , et al. November 23, 2 | 2021-11-23 |
3d Ic Power Grid
App 20210351110 - Mohamed; Noor E.V. ; et al. | 2021-11-11 |
Placement constraint method for multiple patterning of cell-based chip design
Grant 11,170,149 - Wang , et al. November 9, 2 | 2021-11-09 |
Integrated Circuit Fin Layout Method
App 20210342514 - HUANG; Po-Hsiang ; et al. | 2021-11-04 |
Inter-wire Cavity For Low Capacitance
App 20210335655 - Hsueh; Hsiu-Wen ; et al. | 2021-10-28 |
Barrier Free Interface Between Beol Interconnects
App 20210335663 - Hsueh; Hsiu-Wen ; et al. | 2021-10-28 |
Electromagnetic Shielding Metal-insulator-metal Capacitor Structure
App 20210320072 - LEE; Hui Yu ; et al. | 2021-10-14 |
Semiconductor device with filler cell region, method of generating layout diagram and system for same
Grant 11,138,360 - Huang , et al. October 5, 2 | 2021-10-05 |
Integrated circuit layout method and system
Grant 11,138,362 - Huang , et al. October 5, 2 | 2021-10-05 |
Antenna Effect Protection and Electrostatic Discharge Protection for Three-Dimensional Integrated Circuit
App 20210305678 - Huang; Po-Hsiang ; et al. | 2021-09-30 |
Integrated Circuit, Semiconductor Device And Method Of Manufacturing Same
App 20210305213 - CHEN; Chih-Lin ; et al. | 2021-09-30 |
Method of modifying cell, system for modifying cell and global connection routing method
Grant 11,132,488 - Chen , et al. September 28, 2 | 2021-09-28 |
Method For Manufacturing A Cell Having Pins And Semiconductor Device Based On Same
App 20210294957 - SUE; Pin-Dai ; et al. | 2021-09-23 |
Pin Modification For Standard Cells
App 20210265336 - CHANG; Fong-yuan ; et al. | 2021-08-26 |
Nitrogen Plasma Treatment For Improving Interface Between Etch Stop Layer And Copper Interconnect
App 20210257293 - Lee; Hui ; et al. | 2021-08-19 |
Heat dissipation structure including stacked chips surrounded by thermal interface material rings
Grant 11,094,608 - Huang , et al. August 17, 2 | 2021-08-17 |
Electromagnetic shielding metal-insulator-metal capacitor structure
Grant 11,088,084 - Lee , et al. August 10, 2 | 2021-08-10 |
3D IC power grid
Grant 11,081,426 - Mohamed , et al. August 3, 2 | 2021-08-03 |
Integrated circuit fin layout method, system, and structure
Grant 11,080,453 - Huang , et al. August 3, 2 | 2021-08-03 |
Cell Structures And Semiconductor Devices Having Same
App 20210224460 - CHANG; Fong-Yuan ; et al. | 2021-07-22 |
Integrated Circuit And Method Of Generating Integrated Circuit Layout
App 20210217743 - CHANG; Fong-Yuan ; et al. | 2021-07-15 |
Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same
Grant 11,043,473 - Chen , et al. June 22, 2 | 2021-06-22 |
Pin modification for standard cells
Grant 11,037,920 - Chang , et al. June 15, 2 | 2021-06-15 |
Through-Silicon Vias in Integrated Circuit Packaging
App 20210173998 - CHANG; Fong-yuan ; et al. | 2021-06-10 |
Method for generating layout diagram including cell having pin patterns and semiconductor device based on same
Grant 11,030,372 - Sue , et al. June 8, 2 | 2021-06-08 |
Method For Generating Layout Diagram Including Protruding Pin Cell Regions And Semiconductor Device Based On Same
App 20210110097 - CHANG; Fong-Yuan ; et al. | 2021-04-15 |
Cell structures and semiconductor devices having same
Grant 10,970,450 - Chang , et al. April 6, 2 | 2021-04-06 |
E-Fuse Enhancement By Underlayer Layout Design
App 20210098372 - Fu; An-Jiao ; et al. | 2021-04-01 |
Integrated circuit and method of generating integrated circuit layout
Grant 10,964,685 - Chang , et al. March 30, 2 | 2021-03-30 |
Semiconductor Device and Method of Manufacture
App 20210082816 - Chang; Fong-yuan ; et al. | 2021-03-18 |
Integrated Circuit Device With Improved Layout
App 20210082960 - Chang; Fong-yuan ; et al. | 2021-03-18 |
Semiconductor Device Having Fuse Array And Method Of Making The Same
App 20210082812 - CHANG; Meng-Sheng ; et al. | 2021-03-18 |
Through-silicon vias in integrated circuit packaging
Grant 10,949,597 - Chang , et al. March 16, 2 | 2021-03-16 |
Interconnect Structure, Semiconductor Structure Including Interconnect Structure And Method For Forming The Same
App 20210066223 - TSAI; JUNG-CHOU ; et al. | 2021-03-04 |
Method Of Designing A Device
App 20210034807 - CHEN; Sheng-Hsiung ; et al. | 2021-02-04 |
Integrated Circuit Having a High Cell Density
App 20210028108 - Chen; Sheng-Hsiung ; et al. | 2021-01-28 |
Integrated circuit device with improved layout
Grant 10,903,239 - Chang , et al. January 26, 2 | 2021-01-26 |
Integrated Circuit Layout Method And System
App 20200410154 - HUANG; Po-Hsiang ; et al. | 2020-12-31 |
Integrated Circuit And Method Of Forming An Integrated Circuit
App 20200411503 - CHANG; Fong-Yuan ; et al. | 2020-12-31 |
Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same
Grant 10,878,165 - Chang , et al. December 29, 2 | 2020-12-29 |
Package Structure And Method For Forming The Same
App 20200395281 - CHIEN; CHIN-HER ; et al. | 2020-12-17 |
Standard Cells And Variations Thereof Within A Standard Cell Library
App 20200328202 - CHEN; Sheng-Hsiung ; et al. | 2020-10-15 |
Integrated circuit having a high cell density
Grant 10,804,200 - Chen , et al. October 13, 2 | 2020-10-13 |
Method and system for pin layout
Grant 10,796,060 - Chang , et al. October 6, 2 | 2020-10-06 |
Integrated circuit, system for and method of forming an integrated circuit
Grant 10,797,041 - Chang , et al. October 6, 2 | 2020-10-06 |
Method of fabricating integrated circuit having staggered conductive features
Grant 10,777,505 - Chang , et al. Sept | 2020-09-15 |
Integrated circuit structure
Grant 10,776,557 - Huang , et al. Sept | 2020-09-15 |
Electromagnetic Shielding Metal-insulator-metal Capacitor Structure
App 20200258846 - A1 | 2020-08-13 |
Standard cells and variations thereof within a standard cell library
Grant 10,741,539 - Chen , et al. A | 2020-08-11 |
Soic Chip Architecture
App 20200168527 - CHANG; Fong-Yuan ; et al. | 2020-05-28 |
Method Of Modifying Cell, System For Modifying Cell And Global Connection Routing Method
App 20200167518 - CHEN; Sheng-Hsiung ; et al. | 2020-05-28 |
Layout Design Methodology For Stacked Devices
App 20200168595 - CHANG; Fong-Yuan ; et al. | 2020-05-28 |
Electromagnetic shielding metal-insulator-metal capacitor structure
Grant 10,665,550 - Lee , et al. | 2020-05-26 |
Pin Modification For Standard Cells
App 20200152617 - CHANG; Fong-Yuan ; et al. | 2020-05-14 |
Power gating for three dimensional integrated circuits (3DIC)
Grant 10,643,986 - Chao , et al. | 2020-05-05 |
Integrated Circuit Fin Layout Method, System, And Structure
App 20200134122 - HUANG; Po-Hsiang ; et al. | 2020-04-30 |
Method For Generating Layout Diagram Including Cell Having Pin Patterns And Semiconductor Device Based On Same
App 20200134124 - SUE; Pin-Dai ; et al. | 2020-04-30 |
Semiconductor Device With Filler Cell Region, Method Of Generating Layout Diagram And System For Same
App 20200134125 - HUANG; Po-Hsiang ; et al. | 2020-04-30 |
Integrated Circuit, Semiconductor Device And Method Of Manufacturing Same
App 20200126952 - CHEN; Chih-Lin ; et al. | 2020-04-23 |
Integrated Circuit And Method Of Generating Integrated Circuit Layout
App 20200126967 - CHANG; Fong-Yuan ; et al. | 2020-04-23 |
Placement Constraint Method for Multiple Patterning of Cell-Based Chip Design
App 20200089840 - WANG; Shao-Huan ; et al. | 2020-03-19 |
Pin modification for standard cells
Grant 10,559,558 - Chang , et al. Feb | 2020-02-11 |
Interposer With Capacitors
App 20200043873 - CHANG; Fong-yuan ; et al. | 2020-02-06 |
3d Ic Power Grid
App 20200043832 - Mohamed; Noor E.V. ; et al. | 2020-02-06 |
Method of modifying cell and global connection routing method
Grant 10,552,568 - Chen , et al. Fe | 2020-02-04 |
Electromagnetic Shielding Metal-insulator-metal Capacitor Structure
App 20200020644 - LEE; Hui Yu ; et al. | 2020-01-16 |
Through-silicon Vias In Integrated Circuit Packaging
App 20200019668 - CHANG; Fong-yuan ; et al. | 2020-01-16 |
Method For Generating Layout Diagram Including Protruding Pin Cell Regions And Semiconductor Device Based On Same
App 20200019670 - CHANG; Fong-Yuan ; et al. | 2020-01-16 |
Through Silicon Via Optimization For Three-dimensional Integrated Circuits
App 20200020635 - CHANG; Fong-Yuan ; et al. | 2020-01-16 |
Second semiconductor wafer attached to a first semiconductor wafer with a through hole connected to an inductor
Grant 10,535,635 - Chen , et al. Ja | 2020-01-14 |
Heat Dissipation Structures
App 20200006194 - HUANG; Po-Hsiang ; et al. | 2020-01-02 |
Placement constraint method for multiple patterning of cell-based chip design
Grant 10,521,545 - Wang , et al. Dec | 2019-12-31 |
Integrated circuit and method of generating integrated circuit layout
Grant 10,515,944 - Chang , et al. Dec | 2019-12-24 |
A Second Semiconductor Wafer Attached To A First Semiconductor Wafer With A Through Hole Connected To An Inductor
App 20190385980 - CHEN; Chih-Lin ; et al. | 2019-12-19 |
Method For Generating Layout Diagram Including Wiring Arrangement
App 20190286784 - CHANG; Fong-Yuan ; et al. | 2019-09-19 |
Integrated circuit layout methods, structures, and systems
Grant 10,402,534 - Huang , et al. Sep | 2019-09-03 |
Circuit with combined cells and method for manufacturing the same
Grant 10,396,063 - Chang , et al. A | 2019-08-27 |
Method And System For Pin Layout
App 20190243940 - CHANG; FONG-YUAN ; et al. | 2019-08-08 |
Integrated Circuit Structure
App 20190171788 - HUANG; Po-Hsiang ; et al. | 2019-06-06 |
Integrated circuit having staggered conductive features
Grant 10,312,192 - Chang , et al. | 2019-06-04 |
Integrated Circuit And Method Of Generating Integrated Circuit Layout
App 20190148352 - CHANG; Fong-Yuan ; et al. | 2019-05-16 |
Method and system for pin layout
Grant 10,268,796 - Chang , et al. | 2019-04-23 |
Integrated circuit, system for and method of forming an integrated circuit
Grant 10,262,981 - Chang , et al. | 2019-04-16 |
Pin Modification For Standard Cells
App 20190103392 - CHANG; Fong-yuan ; et al. | 2019-04-04 |
Method Of Fabricating Integrated Circuit Having Staggered Conductive Features
App 20190096807 - Chang; Fong-Yuan ; et al. | 2019-03-28 |
Integrated Circuit Having a High Cell Density
App 20190096805 - Chen; Sheng-Hsiung ; et al. | 2019-03-28 |
Integrated Circuit Layout Methods, Structures, And Systems
App 20190095573 - HUANG; Po-Hsiang ; et al. | 2019-03-28 |
Integrated Circuit, System For And Method Of Forming An Integrated Circuit
App 20190096872 - CHANG; Fong-Yuan ; et al. | 2019-03-28 |
Standard Cells and Variations Thereof Within a Standard Cell Library
App 20190064770 - CHEN; Sheng-Hsiung ; et al. | 2019-02-28 |
Integrated Circuit Device With Improved Layout
App 20190035811 - Chang; Fong-yuan ; et al. | 2019-01-31 |
Method for adjusting exposures of multiple camera modules of a camera device
Grant 10,187,585 - Guo , et al. Ja | 2019-01-22 |
Power Gating for Three Dimensional Integrated Circuits (3DIC)
App 20190006346 - Chao; Chien-Ju ; et al. | 2019-01-03 |
Integrated circuit having a high cell density
Grant 10,157,840 - Chen , et al. Dec | 2018-12-18 |
Power gating for three dimensional integrated circuits (3DIC)
Grant 10,074,641 - Chao , et al. September 11, 2 | 2018-09-11 |
Integrated Circuit Having a High Cell Density
App 20180158776 - Chen; Sheng-Hsiung ; et al. | 2018-06-07 |
Cell Structures And Semiconductor Devices Having Same
App 20180150592 - CHANG; Fong-Yuan ; et al. | 2018-05-31 |
Method Of Modifying Cell And Global Connection Routing Method
App 20180107780 - CHEN; Sheng-Hsiung ; et al. | 2018-04-19 |
Method And System For Pin Layout
App 20180075181 - CHANG; FONG-YUAN ; et al. | 2018-03-15 |
Power Gating for Three Dimensional Integrated Circuits (3DIC)
App 20180047716 - Chao; Chien-Ju ; et al. | 2018-02-15 |
Method For Adjusting Exposure Of Camera Device
App 20170374257 - GUO; Jiun-In ; et al. | 2017-12-28 |
Global connection routing method and system for performing the same
Grant 9,846,759 - Chen , et al. December 19, 2 | 2017-12-19 |
Integrated Circuit Having Staggered Conductive Features
App 20170352623 - CHANG; Fong-Yuan ; et al. | 2017-12-07 |
Circuit With Combined Cells And Method For Manufacturing The Same
App 20170345809 - CHANG; FONG-YUAN ; et al. | 2017-11-30 |
Integrated Circuit, System For And Method Of Forming An Integrated Circuit
App 20170317063 - CHANG; Fong-Yuan ; et al. | 2017-11-02 |
Power gating for three dimensional integrated circuits (3DIC)
Grant 9,799,639 - Chao , et al. October 24, 2 | 2017-10-24 |
Placement Constraint Method for Multiple Patterning of Cell-Based Chip Design
App 20170300610 - Wang; Shao-Huan ; et al. | 2017-10-19 |
3D device modeling for FinFET devices
Grant 9,582,633 - Fu , et al. February 28, 2 | 2017-02-28 |
Global Connection Routing Method And System For Performing The Same
App 20170032073 - CHEN; Sheng-Hsiung ; et al. | 2017-02-02 |
Power Gating for Three Dimensional Integrated Circuits (3DIC)
App 20160197068 - Chao; Chien-Ju ; et al. | 2016-07-07 |
Power gating for three dimensional integrated circuits (3DIC)
Grant 9,287,257 - Chao , et al. March 15, 2 | 2016-03-15 |
Power Gating for Three Dimensional Integrated Circuits (3DIC)
App 20150348962 - Chao; Chien-Ju ; et al. | 2015-12-03 |
Method of making a semiconductor device including barrier layers for copper interconnect
Grant 8,975,749 - Liu , et al. March 10, 2 | 2015-03-10 |
3d Device Modeling For Finfet Devices
App 20150026657 - Fu; Chung-min ; et al. | 2015-01-22 |
Thermal analysis of integrated circuit packages
Grant 8,782,593 - Fu , et al. July 15, 2 | 2014-07-15 |
Method Of Making A Semiconductor Device Including Barrier Layers For Copper Interconnect
App 20140127898 - LIU; Nai-Wei ; et al. | 2014-05-08 |
System and method for across-chip thermal and power management in stacked IC designs
Grant 8,701,073 - Fu , et al. April 15, 2 | 2014-04-15 |
System And Method For Across-chip Thermal And Power Management In Stacked Ic Designs
App 20140096102 - FU; Chung-min ; et al. | 2014-04-03 |
Thermal Analysis of Integrated Circuit Packages
App 20140089876 - Fu; Chung-Min ; et al. | 2014-03-27 |
Barrier layers for copper interconnect
Grant 8,653,664 - Liu , et al. February 18, 2 | 2014-02-18 |
Chip-to-chip multi-signaling communication system with common conductive layer
Grant 8,426,980 - Su , et al. April 23, 2 | 2013-04-23 |
Chip-to-chip Multi-signaling Communication System With Common Conductive Layer
App 20120091596 - SU; Chau-Chin ; et al. | 2012-04-19 |
Optical Disc Drive
App 20110276988 - Huang; Po-Hsiang ; et al. | 2011-11-10 |
Barrier Layers For Copper Interconnect
App 20110006429 - LIU; Nai-Wei ; et al. | 2011-01-13 |
LIGHT SOURCE SYSTEM WITH LEDs AND DRIVING METHOD THEREOF
App 20080079705 - Yang; Chien-Yi ; et al. | 2008-04-03 |
Projection Apparatus
App 20070229780 - YANG; CHEN-YI ; et al. | 2007-10-04 |
Projection Device
App 20070085976 - Yang; Chien-Yi ; et al. | 2007-04-19 |
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