name:-0.020128965377808
name:-0.013717889785767
name:-0.0053191184997559
Huang; Liu Patent Filings

Huang; Liu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Huang; Liu.The latest application filed is for "superhydrophobic hemispherical array which can realize droplet pancake bouncing phenomenon".

Company Profile
3.17.17
  • Huang; Liu - Dalian CN
  • Huang; Liu - Pleasanton CA
  • HUANG; Liu - Dalian City Liaoning Province
  • Huang; Liu - Singapore SG
  • Huang; Liu - Malta NY US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks
Patent Activity
PatentDate
Thermal extrusion method to fabricate large-dimension superhydrophobic cylinder pillar arrays with droplet pancake bouncing phenomenon
Grant 11,104,043 - Song , et al. August 31, 2
2021-08-31
Superhydrophobic Hemispherical Array Which Can Realize Droplet Pancake Bouncing Phenomenon
App 20210155837 - SONG; Jinlong ;   et al.
2021-05-27
Device location classification using data collected by wireless access points
Grant 10,721,708 - Mukherji , et al.
2020-07-21
Thermal Extrusion Method To Fabricate Large-dimension Superhydrophobic Cylinder Pillar Arrays With Droplet Pancake Bouncing Phen
App 20200009763 - SONG; Jinlong ;   et al.
2020-01-09
Accurate detection of rogue wireless access points
Grant 10,334,445 - Hooda , et al.
2019-06-25
Accurate Detection Of Rogue Wireless Access Points
App 20170111360 - Hooda; Sanjay Kumar ;   et al.
2017-04-20
Hybrid TSV and method for forming the same
Grant 9,269,651 - Hong , et al. February 23, 2
2016-02-23
Hybrid Tsv And Method For Forming The Same
App 20150179547 - Hong; Yu ;   et al.
2015-06-25
Hybrid TSV and method for forming the same
Grant 9,006,102 - Hong , et al. April 14, 2
2015-04-14
Interconnect formation using a sidewall mask layer
Grant 8,916,472 - Hu , et al. December 23, 2
2014-12-23
Interconnect Formation Using A Sidewall Mask Layer
App 20140038412 - Hu; Xiang ;   et al.
2014-02-06
Scheme for planarizing through-silicon vias
Grant 8,354,327 - Zengxiang , et al. January 15, 2
2013-01-15
Scheme For Planarizing Through-silicon Vias
App 20120270391 - Zengxiang; Chen ;   et al.
2012-10-25
Hybrid TSV and Method for Forming the Same
App 20120267788 - Hong; Yu ;   et al.
2012-10-25
Composite barrier/etch stop layer comprising oxygen doped SiC and SiC for interconnect structures
Grant 7,538,353 - Huang , et al. May 26, 2
2009-05-26
Modulation of Stress in ESL SiN Film through UV Curing to Enhance both PMOS and NMOS Transistor Performance
App 20080124855 - Widodo; Johnny ;   et al.
2008-05-29
Preventing plasma induced damage resulting from high density plasma deposition
Grant 7,208,426 - Huang , et al. April 24, 2
2007-04-24
Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics
Grant 7,186,640 - Huang , et al. March 6, 2
2007-03-06
Use of phoslon (PNO) for borderless contact fabrication, etch stop/barrier layer for dual damascene fabrication and method of forming phoslon
Grant 7,148,157 - Choo , et al. December 12, 2
2006-12-12
Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication
App 20060202343 - Huang; Liu ;   et al.
2006-09-14
Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication
Grant 7,052,932 - Huang , et al. May 30, 2
2006-05-30
Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication
App 20050184295 - Huang, Liu ;   et al.
2005-08-25
Deposition and sputter etch approach to extend the gap fill capability of HDP CVD process to .ltoreq.0.10 microns
Grant 6,872,633 - Huang , et al. March 29, 2
2005-03-29
Use of amorphous carbon as a removable ARC material for dual damascene fabrication
Grant 6,787,452 - Sudijono , et al. September 7, 2
2004-09-07
Use of amorphous carbon as a removable ARC material for dual damascene fabrication
App 20040092098 - Sudijono, John ;   et al.
2004-05-13
Use of phoslon (PNO) for borderless contact fabrication, etch stop/barrier layer for dual damascene fabrication and method of forming phoslon
App 20040077181 - Choo, Hsia Liang ;   et al.
2004-04-22
HDP SRO liner for beyond 0.18 um STI gap-fill
App 20040005781 - Huang, Liu ;   et al.
2004-01-08
Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics
App 20030235980 - Huang, Liu ;   et al.
2003-12-25
Novel deposition and sputter etch approach to extend the gap fill capability of HDP CVD process to less than or equal to 0.10 microns
App 20030224580 - Huang, Liu ;   et al.
2003-12-04
Preventing plasma induced damage resulting from high density plasma deposition
App 20030092284 - Huang, Liu ;   et al.
2003-05-15

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