Huang; Lan Ting

Patent Applications and Registrations

Patent applications and USPTO patent grants for Huang; Lan Ting.The latest application filed is for "semiconductor memory device bit line transistor with discrete gate".

Company Profile

0.8.8

Huang; Lan Ting - Hsin-Chu TW
Huang; Lan Ting - Kaohsiung TW
Huang; Lan-Ting - Hsinchu TW
Huang; Lan-Ting - Hsinchu City TW
Huang; Lan-Ting - Hsin-Chu City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor Memory Device Bit Line Transistor With Discrete Gate App 20160307836 - TSai; Ya Jung ; et al.	2016-10-20
Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate Grant 8,354,335 - Liu , et al. January 15, 2	2013-01-15
Apparatus And Associated Method For Making A Floating Gate Cell With Increased Overlay Between The Control Gate And Floating Gate App 20110086482 - Liu; Chen-Chin ; et al.	2011-04-14
Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate Grant 7,879,708 - Liu , et al. February 1, 2	2011-02-01
Erase operation for use in non-volatile memory Grant 7,403,430 - Liu , et al. July 22, 2	2008-07-22
Apparatus And Associated Method For Making A Floating Gate Cell With Increased Overlay Between The Control Gate And Floating Gate App 20080121971 - Liu; Chen-Chin ; et al.	2008-05-29
Bit line selection transistor layout structure Grant 7,286,396 - Yang , et al. October 23, 2	2007-10-23
Erase operation for use in non-volatile memory App 20070189080 - Liu; Cheng-Jye ; et al.	2007-08-16
Bit line selection transistor layout structure App 20070081383 - Yang; Ling Kuey ; et al.	2007-04-12
Memory array including isolation between memory cell and dummy cell portions Grant 7,183,608 - Huang , et al. February 27, 2	2007-02-27
Memory array including isolation between memory cell and dummy cell portions App 20060267079 - Huang; Lan-Ting ; et al.	2006-11-30
Method for forming non-volatile memory cell with low-temperature-formed dielectric between word and bit lines, and non-volatile memory array including such memory cells Grant 7,064,032 - Hsu , et al. June 20, 2	2006-06-20
Word line strap layout structure Grant 6,909,131 - Liu , et al. June 21, 2	2005-06-21
Method for forming non-volatile memory cell with low-temperature-formed dielectric between word and bit lines, and non-volatile memory array including such memory cells App 20050020010 - Hsu, Fu Shiung ; et al.	2005-01-27
Word Line Strap Layout Structure App 20040238863 - Liu, Chen-Chin ; et al.	2004-12-02

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