Huang; Jing-Reng
Patent Applications and Registrations
Patent applications and USPTO patent grants for Huang; Jing-Reng.The latest application filed is for "method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect".
- Huang; Jing-Reng - Hsinchu TW
- Huang; Jing-Reng - Pingtung TW
- Huang; Jing-Reng - Hsin-Chu TW
| Patent | Date |
|---|---|
| Test pattern generator for SRAM and DRAM Grant 6,934,900 - Cheng , et al. August 23, 2 | 2005-08-23 |
| Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect Grant 6,914,471 - Chang , et al. July 5, 2 | 2005-07-05 |
| Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect App 20050024120 - Chang, Tsin-Yuan ; et al. | 2005-02-03 |
| Programmable built in self test for embedded DRAM Grant 6,415,403 - Huang , et al. July 2, 2 | 2002-07-02 |
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