Huang; Hsin-Chien

Patent Applications and Registrations

Patent applications and USPTO patent grants for Huang; Hsin-Chien.The latest application filed is for "cancer treatment by in vitro amino acid deprivation".

Company Profile

2.9.12

Huang; Hsin-Chien - New Taipei City TW
Huang; Hsin-Chien - Hsinchu City TW
Huang; Hsin-Chien - Tainan TW
Huang; Hsin-Chien - Tainan City TW
Huang; Hsin-Chien - Hsinchu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Cancer Treatment By In Vitro Amino Acid Deprivation App 20220305178 - Shih; Tsung-Ping ; et al.	2022-09-29
Intelligent Store System And Intelligent Store Method App 20220138838 - Chiang; Chi-Chou ; et al.	2022-05-05
Intelligent Storage Device And Intelligent Storage Method App 20220137256 - Huang; Hsin-Chien ; et al.	2022-05-05
Method and device for analyzing data Grant 11,086,881 - Huang , et al. August 10, 2	2021-08-10
Intelligent Planogram Producing System And Method Thereof App 20210182774 - CHIANG; Chi-Chou ; et al.	2021-06-17
Storage device and storage method to identify object using sensing data and identification model Grant 10,984,376 - Huang , et al. April 20, 2	2021-04-20
Storage Device And Storage Method App 20200076893 - Huang; Hsin-Chien ; et al.	2020-03-05
Data Analysis Method, System And Non-transitory Computer Readable Medium App 20180150754 - Huang; Hsin-Chien ; et al.	2018-05-31
Method And Device For Analyzing Data App 20170083583 - HUANG; Hsin-Chien ; et al.	2017-03-23
Method for fabrication of wafer level package incorporating dual compliant layers Grant 7,329,563 - Lo , et al. February 12, 2	2008-02-12
Inkjet printhead App 20050280670 - Chuang, Sway ; et al.	2005-12-22
Method for fabrication of wafer level package incorporating dual compliant layers App 20050260794 - Lo, Wei-Chung ; et al.	2005-11-24
Method for assembling carbon nanotubes and microprobe and an apparatus thereof App 20050150767 - Su, Hui-Chi ; et al.	2005-07-14
Wafer level package incorporating dual compliant layers and method for fabrication Grant 6,914,333 - Lo , et al. July 5, 2	2005-07-05
Wafer level package incorporating dual compliant layers and method for fabrication App 20040043538 - Lo, Wei-Chung ; et al.	2004-03-04
Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer Grant 6,459,150 - Wu , et al. October 1, 2	2002-10-01
Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication Grant 6,433,427 - Wu , et al. August 13, 2	2002-08-13
Wafer Level Package Incorporating Dual Stress Buffer Layers For I/o Redistribution App 20020093107 - Wu, Enboa ; et al.	2002-07-18
Wafer level package incorporating elastomeric pads in dummy plugs Grant 6,358,836 - Lu , et al. March 19, 2	2002-03-19
Simultaneous bumping/bonding process utilizing edge-type conductive pads and device fabricated Grant 6,312,974 - Wu , et al. November 6, 2	2001-11-06
Built-in stress pattern on IC dies and method of forming Grant 6,218,726 - Chang , et al. April 17, 2	2001-04-17

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