Huang; Elbert E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Huang; Elbert E..The latest application filed is for "selective recessing to form a fully aligned via".

Company Profile

12.79.70

Huang; Elbert E. - Carmel NY
Huang; Elbert E. - Mountain View CA
Huang; Elbert E. - Santa Clara CA
Huang; Elbert E - Carmel NY US
Huang; Elbert E. - Yorktown Heights NY
Huang; Elbert E. - Tarrytown NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Selective recessing to form a fully aligned via Grant 11,257,717 - Briggs , et al. February 22, 2	2022-02-22
Selective Recessing To Form A Fully Aligned Via App 20210082758 - Briggs; Benjamin D. ; et al.	2021-03-18
Selective recessing to form a fully aligned via Grant 10,832,952 - Briggs , et al. November 10, 2	2020-11-10
Low aspect ratio interconnect Grant 10,672,707 - Briggs , et al.	2020-06-02
Selective recessing to form a fully aligned via Grant 10,636,706 - Briggs , et al.	2020-04-28
Interconnect structures with fully aligned vias Grant 10,607,933 - Edelstein , et al.	2020-03-31
Interconnect Structures With Fully Aligned Vias App 20190157201 - Edelstein; Daniel C. ; et al.	2019-05-23
Low Aspect Ratio Interconnect App 20190148296 - Briggs; Benjamin D. ; et al.	2019-05-16
Selective recessing to form a fully aligned via Grant 10,276,436 - Briggs , et al.	2019-04-30
Interconnect structure having subtractive etch feature and damascene feature Grant 10,256,186 - Bonilla , et al.	2019-04-09
Forming air gap Grant 10,224,236 - Choi , et al.	2019-03-05
Low aspect ratio interconnect Grant 10,211,153 - Briggs , et al. Feb	2019-02-19
Interconnect structures with fully aligned vias Grant 10,204,856 - Edelstein , et al. Feb	2019-02-12
Selective Recessing To Form A Fully Aligned Via App 20180315653 - Briggs; Benjamin D. ; et al.	2018-11-01
Selective Recessing To Form A Fully Aligned Via App 20180315654 - Briggs; Benjamin D. ; et al.	2018-11-01
Detecting a void between a via and a wiring line Grant 10,103,068 - Bonilla , et al. October 16, 2	2018-10-16
Selective and non-selective barrier layer wet removal Grant 10,002,831 - Briggs , et al. June 19, 2	2018-06-19
Air gap semiconductor structure with selective cap bilayer Grant 9,960,117 - Gates , et al. May 1, 2	2018-05-01
Barrier Planarization For Interconnect Metallization App 20180114719 - Briggs; Benjamin D. ; et al.	2018-04-26
Barrier Planarization For Interconnect Metallization App 20180114718 - Briggs; Benjamin D. ; et al.	2018-04-26
Interconnect Structures With Fully Aligned Vias App 20180102317 - Edelstein; Daniel C. ; et al.	2018-04-12
Interconnect Scaling App 20180076133 - BONILLA; Griselda ; et al.	2018-03-15
Forming Air Gap App 20180076082 - Choi; Samuel S. ; et al.	2018-03-15
Interconnect structures with fully aligned vias Grant 9,911,690 - Edelstein , et al. March 6, 2	2018-03-06
Low Aspect Ratio Interconnect App 20180061761 - Briggs; Benjamin D. ; et al.	2018-03-01
Selective Recessing To Form A Fully Aligned Via App 20180040510 - Briggs; Benjamin D. ; et al.	2018-02-08
Barrier planarization for interconnect metallization Grant 9,881,833 - Briggs , et al. January 30, 2	2018-01-30
Interconnect structure having substractive etch feature and damascene feature Grant 9,852,980 - Bonilla , et al. December 26, 2	2017-12-26
Forming Air Gap App 20170365504 - Choi; Samuel S. ; et al.	2017-12-21
Selective And Non-selective Barrier Layer Wet Removal App 20170317026 - Briggs; Benjamin D. ; et al.	2017-11-02
Selective and non-selective barrier layer wet removal Grant 9,806,023 - Briggs , et al. October 31, 2	2017-10-31
Selective And Non-selective Barrier Layer Wet Removal App 20170301624 - Briggs; Benjamin D. ; et al.	2017-10-19
Electromigration test structure for Cu barrier integrity and blech effect evaluations Grant 9,759,766 - Bonilla , et al. September 12, 2	2017-09-12
Interconnect Scaling App 20170221815 - Bonilla; Griselda ; et al.	2017-08-03
Method of forming an air gap semiconductor structure with selective cap bilayer Grant 9,711,455 - Gates , et al. July 18, 2	2017-07-18
Electromigration Test Structure For Cu Barrier Integrity And Blech Effect Evaluations App 20170176514 - BONILLA; GRISELDA ; et al.	2017-06-22
Selective and non-selective barrier layer wet removal Grant 9,685,406 - Briggs , et al. June 20, 2	2017-06-20
Interconnect structure having subtractive etch feature and damascene feature Grant 9,601,426 - Bonilla , et al. March 21, 2	2017-03-21
Detecting A Void Between A Via And A Wiring Line App 20160370421 - Bonilla; Griselda ; et al.	2016-12-22
Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer Grant 9,502,350 - Bonilla , et al. November 22, 2	2016-11-22
Electromigration test structure for Cu barrier integrity and blech effect evaluations Grant 9,472,477 - Bonilla , et al. October 18, 2	2016-10-18
Alternate dual damascene method for forming interconnects Grant 9,431,292 - Bonilla , et al. August 30, 2	2016-08-30
Interconnect Structures With Fully Aligned Vias App 20160163640 - Edelstein; Daniel C. ; et al.	2016-06-09
Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect Grant 9,349,687 - Gates , et al. May 24, 2	2016-05-24
Air Gap Structure With Bilayer Selective Cap App 20160133508 - Gates; Stephen M. ; et al.	2016-05-12
Air Gap Structure With Bilayer Selective Cap App 20160133575 - Gates; Stephen M. ; et al.	2016-05-12
Microelectronic structure including air gap Grant 9,332,628 - Edelstein , et al. May 3, 2	2016-05-03
Interconnect structures with fully aligned vias Grant 9,324,650 - Edelstein , et al. April 26, 2	2016-04-26
Air gap semiconductor structure with selective cap bilayer Grant 9,305,836 - Gates , et al. April 5, 2	2016-04-05
Multimetal Interlayer Interconnects App 20160071791 - Huang; Elbert E. ; et al.	2016-03-10
Structure With Self Aligned Resist Layer On An Interconnect Surface And Method Of Making Same App 20160056106 - EDELSTEIN; Daniel C. ; et al.	2016-02-25
Interconnect Structures With Fully Aligned Vias App 20160049364 - Edelstein; Daniel C. ; et al.	2016-02-18
Structure with self aligned resist layer on an interconnect surface and method of making same Grant 9,202,863 - Edelstein , et al. December 1, 2	2015-12-01
Microelectronic Structure Including Air Gap App 20150289361 - Edelstein; Daniel C. ; et al.	2015-10-08
Microelectronic structure including air gap Grant 9,105,693 - Edelstein , et al. August 11, 2	2015-08-11
Corrugated interfaces for multilayered interconnects Grant 9,089,080 - Clevenger , et al. July 21, 2	2015-07-21
Vertical electronic fuse Grant 9,064,871 - Bao , et al. June 23, 2	2015-06-23
Microelectronic structure including air gap Grant 9,059,251 - Edelstein , et al. June 16, 2	2015-06-16
Vertical Electronic Fuse App 20140332856 - Bao; Junjing ; et al.	2014-11-13
Sealed air gap for semiconductor chip Grant 8,871,624 - Horak , et al. October 28, 2	2014-10-28
Corrugated interfaces for multilayered interconnects Grant 8,828,521 - Clevenger , et al. September 9, 2	2014-09-09
Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer Grant 8,809,183 - Bonilla , et al. August 19, 2	2014-08-19
Corrugated Interfaces For Multilayered Interconnects App 20130270224 - Clevenger; Lawrence A. ; et al.	2013-10-17
Corrugated Interfaces For Multilayered Interconnects App 20130273325 - Clevenger; Lawrence A. ; et al.	2013-10-17
Structure including voltage controlled negative resistance Grant 8,525,153 - Chen , et al. September 3, 2	2013-09-03
Corrugated interfaces for multilayered interconnects Grant 8,512,849 - Clevenger , et al. August 20, 2	2013-08-20
Structure With Self Aligned Resist Layer On An Interconnect Surface And Method Of Making Same App 20130193551 - EDELSTEIN; Daniel C. ; et al.	2013-08-01
Structure For Nano-scale Metallization And Method For Fabricating Same App 20130193579 - Ponoth; Shom ; et al.	2013-08-01
Structure for nano-scale metallization and method for fabricating same Grant 8,492,270 - Ponoth , et al. July 23, 2	2013-07-23
Design Structure Including Voltage Controlled Negative Resistance App 20130146940 - Chen; Fen ; et al.	2013-06-13
Structure with self aligned resist layer on an interconnect surface and method of making same Grant 8,461,678 - Edelstein , et al. June 11, 2	2013-06-11
Sealed Air Gap For Semiconductor Chip App 20130130489 - Horak; David V. ; et al.	2013-05-23
Crenulated wiring structure and method for integrated circuit interconnects Grant 8,421,239 - Bonilla , et al. April 16, 2	2013-04-16
Sealed air gap for semiconductor chip Grant 8,390,079 - Horak , et al. March 5, 2	2013-03-05
Microelectronic Structure Including Air Gap App 20130009282 - Edelstein; Daniel C. ; et al.	2013-01-10
Interconnect Structure Fabricated Without Dry Plasma Etch Processing App 20130009312 - Darnon; Maxime ; et al.	2013-01-10
Microelectronic Structure Including Air Gap App 20130012017 - Edelstein; Daniel C. ; et al.	2013-01-10
Device and methodology for reducing effective dielectric constant in semiconductor devices Grant 8,343,868 - Edelstein , et al. January 1, 2	2013-01-01
Interconnect structure fabricated without dry plasma etch processing Grant 8,298,937 - Darnon , et al. October 30, 2	2012-10-30
Microelectronic structure including air gap Grant 8,288,268 - Edelstein , et al. October 16, 2	2012-10-16
Sealed Air Gap For Semiconductor Chip App 20120199886 - Horak; David V. ; et al.	2012-08-09
Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach Grant 8,232,618 - Breyta , et al. July 31, 2	2012-07-31
Structure with self aligned resist layer on an interconnect surface and method of making same Grant 8,227,336 - Edelstein , et al. July 24, 2	2012-07-24
Structure With Self Aligned Resist Layer On An Interconnect Surface And Method Of Making Same App 20120168953 - EDELSTEIN; Daniel C. ; et al.	2012-07-05
Sealed Air Gap For Semiconductor Chip App 20120104512 - Horak; David V. ; et al.	2012-05-03
Interconnect Structure With A Planar Interface Between A Selective Conductive Cap And A Dielectric Cap Layer App 20120068344 - Bonilla; Griselda ; et al.	2012-03-22
Structure For Nano-scale Metallization And Method For Fabricating Same App 20120068346 - PONOTH; SHOM ; et al.	2012-03-22
Reducing effective dielectric constant in semiconductor devices Grant 8,129,286 - Edelstein , et al. March 6, 2	2012-03-06
Semiconductor Structure Having A Contact-level Air Gap Within The Interlayer Dielectrics Above A Semiconductor Device And A Method Of Forming The Semiconductor Structure Using A Self-assembly Approach App 20120037962 - Breyta; Gregory ; et al.	2012-02-16
Microelectronic Structure Including Air Gap App 20110266682 - Edelstein; Daniel C. ; et al.	2011-11-03
Temporary etchable liner for forming air gap Grant 8,030,202 - Horak , et al. October 4, 2	2011-10-04
Crenulated Wiring Structure And Method For Integrated Circuit Interconnects App 20110227232 - Bonilla; Griselda ; et al.	2011-09-22
Multilayered Cap Barrier In Microelectronic Interconnect Structures App 20110226981 - Hedrick; Jeffrey C. ; et al.	2011-09-22
Structure with self aligned resist layer on an insulating surface and method of making same Grant 7,993,817 - Edelstein , et al. August 9, 2	2011-08-09
Anisotropic stress generation by stress-generating liners having a sublithographic width Grant 7,989,291 - Clevenger , et al. August 2, 2	2011-08-02
Multilayered cap barrier in microelectronic interconnect structures Grant 7,951,705 - Hedrick , et al. May 31, 2	2011-05-31
Sub-lithographic dimensioned air gap formation and related structure Grant 7,943,480 - Edelstein , et al. May 17, 2	2011-05-17
Device And Methodology For Reducing Effective Dielectric Constant In Semiconductor Devices App 20110111590 - Edelstein; Daniel C. ; et al.	2011-05-12
Device and methodology for reducing effective dielectric constant in semiconductor devices Grant 7,892,940 - Edelstein , et al. February 22, 2	2011-02-22
Polycarbosilane buried etch stops in interconnect structures Grant 7,879,717 - Huang , et al. February 1, 2	2011-02-01
Interconnect Structure Fabricated Without Dry Plasma Etch Processing App 20100314768 - Darnon; Maxime ; et al.	2010-12-16
Structure With Self Aligned Resist Layer On An Interconnect Surface And Method Of Making Same App 20100181678 - Edelstein; Daniel C. ; et al.	2010-07-22
Structure With Self Aligned Resist Layer On An Insulating Surface And Method Of Making Same App 20100181677 - Edelstein; Daniel C. ; et al.	2010-07-22
Anisotropic Stress Generation By Stress-generating Liners Having A Sublithographic Width App 20100151638 - Clevenger; Lawrence A. ; et al.	2010-06-17
Anisotropic stress generation by stress-generating liners having a sublithographic width Grant 7,696,542 - Clevenger , et al. April 13, 2	2010-04-13
Method to remove beol sacrificial materials and chemical residues by irradiation Grant 7,598,169 - Lin , et al. October 6, 2	2009-10-06
Device and methodology for reducing effective dielectric constant in semiconductor devices Grant 7,592,685 - Edelstein , et al. September 22, 2	2009-09-22
Sub-lithographic Dimensioned Air Gap Formation And Related Structure App 20090200636 - Edelstein; Daniel C. ; et al.	2009-08-13
Anisotropic Stress Generation By Stress-generating Liners Having A Sublithographic Width App 20090184374 - Clevenger; Lawrence A. ; et al.	2009-07-23
Corrugated Interfaces For Multilayered Interconnects App 20090041989 - Clevenger; Lawrence A. ; et al.	2009-02-12
Method of fabricating a multilayered dielectric diffusion barrier layer Grant 7,470,597 - Hedrick , et al. December 30, 2	2008-12-30
Multilayered Cap Barrier In Microelectronic Interconnect Structures App 20080254614 - Hedrick; Jeffrey C. ; et al.	2008-10-16
Device And Methodology For Reducing Effective Dielectric Constant In Semiconductor Devices App 20080254630 - EDELSTEIN; Daniel C. ; et al.	2008-10-16
Polycarbosilane Buried Etch Stops In Interconnect Structures App 20080254612 - Huang; Elbert E. ; et al.	2008-10-16
Method To Remove Beol Sacrificial Materials And Chemical Residues By Irradiation App 20080200034 - Lin; Qinghuang ; et al.	2008-08-21
Device and methodology for reducing effective dielectric constant in semiconductor devices Grant 7,405,147 - Edelstein , et al. July 29, 2	2008-07-29
Polycarbosilane buried etch stops in interconnect structures Grant 7,396,758 - Huang , et al. July 8, 2	2008-07-08
Mosfet Structure With Ultra-low K Spacer App 20080128766 - Huang; Elbert E. ; et al.	2008-06-05
MOSFET structure with ultra-low K spacer Grant 7,365,378 - Huang , et al. April 29, 2	2008-04-29
Device And Methodology For Reducing Effective Dielectric Constant In Semiconductor Devices App 20080038923 - EDELSTEIN; Daniel C. ; et al.	2008-02-14
Device And Methodology For Reducing Effective Dielectric Constant In Semiconductor Devices App 20080038915 - EDELSTEIN; Daniel C. ; et al.	2008-02-14
Antireflective composition and process of making a lithographic structure Grant 7,326,442 - Babich , et al. February 5, 2	2008-02-05
Method of forming a ceramic diffusion barrier layer Grant 7,256,146 - Cohen , et al. August 14, 2	2007-08-14
Polycarbosilane Buried Etch Stops In Interconnect Structures App 20070111509 - Huang; Elbert E. ; et al.	2007-05-17
Polycarbosilane buried etch stops in interconnect structures Grant 7,187,081 - Huang , et al. March 6, 2	2007-03-06
Antireflective composition and process of making a lithographic structure App 20070015083 - Babich; Katherina E. ; et al.	2007-01-18
MOSFET structure with ultra-low K spacer App 20060220152 - Huang; Elbert E. ; et al.	2006-10-05
Multilayered cap barrier in microelectronic interconnect structures App 20060197224 - Hedrick; Jeffrey C. ; et al.	2006-09-07
Multilayered cap barrier in microelectronic interconnect structures Grant 7,081,673 - Hedrick , et al. July 25, 2	2006-07-25
Interconnect structures incorporating low-k dielectric barrier films App 20050206004 - Cohen, Stephan A. ; et al.	2005-09-22
Interconnect structures incorporating low-k dielectric barrier films Grant 6,940,173 - Cohen , et al. September 6, 2	2005-09-06
Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence Grant 6,930,034 - Colburn , et al. August 16, 2	2005-08-16
Patterning layers comprised of spin-on ceramic films Grant 6,929,982 - Gates , et al. August 16, 2	2005-08-16
Device And Methodology For Reducing Effective Dielectric Constant In Semiconductor Devices App 20050167838 - Edelstein, Daniel C. ; et al.	2005-08-04
Interconnect structures incorporating low-k dielectric barrier films App 20050087876 - Cohen, Stephan A. ; et al.	2005-04-28
Multilayered cap barrier in microelectronic interconnect structures App 20040207084 - Hedrick, Jeffrey C. ; et al.	2004-10-21
Patterning layers comprised of spin-on ceramic films Grant 6,803,660 - Gates , et al. October 12, 2	2004-10-12
Polycarbosilane buried etch stops in interconnect structures App 20040147111 - Huang, Elbert E. ; et al.	2004-07-29
Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence App 20040127001 - Colburn, Matthew E. ; et al.	2004-07-01

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