Huang; Chih Po
Patent Applications and Registrations
Patent applications and USPTO patent grants for Huang; Chih Po.The latest application filed is for "n-well and n+ buried layer isolation by auto doping to reduce chip size".
- Huang; Chih Po - HsinChu TW
- Huang; Chih Po - Hsin-Chu TW
- Huang; Chih Po - HsinChu city TW
| Patent | Date |
|---|---|
| N-well and N.sup.+ buried layer isolation by auto doping to reduce chip size Grant 7,436,043 - Sung , et al. October 14, 2 | 2008-10-14 |
| Method and apparatus for a semiconductor device having low and high voltage transistors Grant 7,205,630 - Chang , et al. April 17, 2 | 2007-04-17 |
| Semiconductor structure for isolating integrated circuits of various operation voltages Grant 7,196,392 - Liu , et al. March 27, 2 | 2007-03-27 |
| N-well and N+ buried layer isolation by auto doping to reduce chip size App 20060133189 - Sung; Tzu-Chiang ; et al. | 2006-06-22 |
| Semiconductor structure for isolating integrated circuits of various operation voltages App 20060113571 - Liu; Jun-Xiu ; et al. | 2006-06-01 |
| Method and apparatus for a semiconductor device having low and high voltage transistors App 20060006462 - Chang; Chi-Hsuen ; et al. | 2006-01-12 |
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