loadpatents
name:-0.13417315483093
name:-0.13404703140259
name:-0.02603006362915
Huang; Cheng-Lin Patent Filings

Huang; Cheng-Lin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Huang; Cheng-Lin.The latest application filed is for "chip package structure with ring-like structure".

Company Profile
26.108.106
  • Huang; Cheng-Lin - Hsinchu TW
  • Huang; Cheng-Lin - Kaohsiung TW
  • HUANG; Cheng-Lin - Hsinchu City TW
  • Huang; Cheng-Lin - Taoyuan City TW
  • Huang; Cheng-Lin - Hsin-Chu TW
  • Huang; Cheng-Lin - Kaohsiung City TW
  • Huang; Cheng-Lin - Kaosiung TW
  • - Hsin-Chu TW
  • Huang; Cheng-Lin - Taipei TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Chip package structure
Grant 11,456,276 - Li , et al. September 27, 2
2022-09-27
Metal oxide layered structure and methods of forming the same
Grant 11,443,957 - Lin , et al. September 13, 2
2022-09-13
Semiconductor die singulation and structures formed thereby
Grant 11,367,658 - Chang , et al. June 21, 2
2022-06-21
Non-vertical through-via in package
Grant 11,355,406 - Huang , et al. June 7, 2
2022-06-07
Charging system with low power consumption
Grant 11,336,106 - Cheng , et al. May 17, 2
2022-05-17
Structure and formation method for chip package
Grant 11,329,031 - Hung , et al. May 10, 2
2022-05-10
Bump layout for coplanarity improvement
Grant 11,211,318 - Li , et al. December 28, 2
2021-12-28
Chip Package Structure With Ring-like Structure
App 20210375821 - YANG; Sheng-Yao ;   et al.
2021-12-02
Chip package structure including ring-like structure and method for forming the same
Grant 11,088,108 - Yang , et al. August 10, 2
2021-08-10
Method For Forming Semiconductor Die Having Edge With Multiple Gradients
App 20210233803 - TANG; Yu-Sheng ;   et al.
2021-07-29
Semiconductor die having edge with multiple gradients and method for forming the same
Grant 11,004,728 - Tang , et al. May 11, 2
2021-05-11
User Verification Method And Mobile Device
App 20210055827 - Huang; Cheng-Lin ;   et al.
2021-02-25
Chip Package Structure And Method For Forming The Same
App 20200411467 - YANG; Sheng-Yao ;   et al.
2020-12-31
Chip Package Structure
App 20200411468 - LI; Ling-Wei ;   et al.
2020-12-31
Semiconductor packaged wafer and method for forming the same
Grant 10,861,761 - Chang , et al. December 8, 2
2020-12-08
Structure and Formation Method for Chip Package
App 20200381407 - Hung; Jui-Pin ;   et al.
2020-12-03
Fan-Out Package and Methods of Forming Thereof
App 20200373264 - Shih; Wan-Ting ;   et al.
2020-11-26
Conductive External Connector Structure and Method of Forming
App 20200373267 - Shih; Meng-Fu ;   et al.
2020-11-26
Semiconductor Die Singulation and Structures Formed Thereby
App 20200350209 - Chang; Fu-Chen ;   et al.
2020-11-05
Non-Vertical Through-via in Package
App 20200303275 - Huang; Cheng-Lin ;   et al.
2020-09-24
Chip package structure and method for forming the same
Grant 10,770,427 - Li , et al. Sep
2020-09-08
Metal Oxide Layered Structure and Methods of Forming the Same
App 20200279750 - Lin; Jing-Cheng ;   et al.
2020-09-03
Structure and formation method for chip package
Grant 10,748,882 - Hung , et al. A
2020-08-18
Conductive external connector structure and method of forming
Grant 10,741,513 - Shih , et al. A
2020-08-11
Fan-out package and methods of forming thereof
Grant 10,741,511 - Shih , et al. A
2020-08-11
Semiconductor die singulation and structures formed thereby
Grant 10,720,360 - Chang , et al.
2020-07-21
Non-vertical through-via in package
Grant 10,699,981 - Huang , et al.
2020-06-30
Metal oxide layered structure and methods of forming the same
Grant 10,658,195 - Lin , et al.
2020-05-19
Semiconductor Die Having Edge With Multiple Gradients And Method For Forming The Same
App 20200152506 - TANG; Yu-Sheng ;   et al.
2020-05-14
Bump Layout For Coplanarity Improvement
App 20200105654 - Li; Ling-Wei ;   et al.
2020-04-02
Semiconductor die having edge with multiple gradients and method for forming the same
Grant 10,535,554 - Tang , et al. Ja
2020-01-14
Semiconductor die singulation and structures formed thereby
Grant 10,510,605 - Chang , et al. Dec
2019-12-17
Fan-Out Package and Methods of Forming Thereof
App 20190355684 - Shih; Wan-Ting ;   et al.
2019-11-21
Methods of forming multiple conductive features in semiconductor devices in a same formation process
Grant 10,446,522 - Lin , et al. Oc
2019-10-15
Charging System With Low Power Consumption
App 20190280486 - Cheng; Hung-Hsuan ;   et al.
2019-09-12
Fan-out package and methods of forming thereof
Grant 10,366,960 - Shih , et al. July 30, 2
2019-07-30
Semiconductor structure having an air-gap region and a method of manufacturing the same
Grant 10,361,152 - Su , et al.
2019-07-23
Conductive External Connector Structure and Method of Forming
App 20190131263 - Shih; Meng-Fu ;   et al.
2019-05-02
Semiconductor Packaged Wafer And Method For Forming The Same
App 20190103389 - CHANG; FU-CHEN ;   et al.
2019-04-04
Non-Vertical Through-via in Package
App 20190067146 - Huang; Cheng-Lin ;   et al.
2019-02-28
Structure and Formation Method for Chip Package
App 20190006332 - Hung; Jui-Pin ;   et al.
2019-01-03
Conductive external connector structure and method of forming
Grant 10,163,836 - Shih , et al. Dec
2018-12-25
Metal oxide layered structure and methods of forming the same
Grant 10,153,175 - Lin , et al. Dec
2018-12-11
Metal Oxide Layered Structure and Methods of Forming the Same
App 20180337062 - Lin; Jing-Cheng ;   et al.
2018-11-22
Solder bump for ball grid array
Grant 10,134,701 - Chang , et al. November 20, 2
2018-11-20
Semiconductor Die Singulation and Structures Formed Thereby
App 20180330991 - Chang; Fu-Chen ;   et al.
2018-11-15
Non-vertical through-via in package
Grant 10,115,647 - Huang , et al. October 30, 2
2018-10-30
Structure and formation method for chip package
Grant 10,074,637 - Hung , et al. September 11, 2
2018-09-11
Method for forming semiconductor device structure with bumps
Grant 10,014,218 - Shih , et al. July 3, 2
2018-07-03
Semiconductor Die Having Edge With Multiple Gradients And Method For Forming The Same
App 20180166328 - TANG; Yu-Sheng ;   et al.
2018-06-14
Conductive External Connector Structure and Method of Forming
App 20180166409 - Shih; Meng-Fu ;   et al.
2018-06-14
Pillar design for conductive bump
Grant 9,953,948 - Hsieh , et al. April 24, 2
2018-04-24
Semiconductor Die Singulation and Structures Formed Thereby
App 20180033695 - Chang; Fu-Chen ;   et al.
2018-02-01
Fan-Out Package and Methods of Forming Thereof
App 20180033747 - Shih; Wan-Ting ;   et al.
2018-02-01
Integrated fan-out package on package structure and methods of forming same
Grant 9,881,908 - Lin , et al. January 30, 2
2018-01-30
Conductive external connector structure and method of forming
Grant 9,875,979 - Shih , et al. January 23, 2
2018-01-23
Chip Package With Thermal Dissipation Structure And Method For Forming The Same
App 20180019183 - WANG; Chin-Hua ;   et al.
2018-01-18
Chip package with thermal dissipation structure and method for forming the same
Grant 9,870,975 - Wang , et al. January 16, 2
2018-01-16
Fan-out package and methods of forming thereof
Grant 9,824,989 - Shih , et al. November 21, 2
2017-11-21
Solder Bump for Ball Grid Array
App 20170317044 - Chang; Jung-Hua ;   et al.
2017-11-02
Semiconductor package assembly, semiconductor package and forming method thereof
Grant 9,748,156 - Yeh , et al. August 29, 2
2017-08-29
Integrated Fan-Out Package on Package Structure and Methods of Forming Same
App 20170207204 - Lin; Wen-Yi ;   et al.
2017-07-20
Bump structural designs to minimize package defects
Grant 9,711,475 - Lin , et al. July 18, 2
2017-07-18
Solder bump for ball grid array
Grant 9,711,472 - Chang , et al. July 18, 2
2017-07-18
Structure and Formation Method for Chip Package
App 20170186736 - Hung; Jui-Pin ;   et al.
2017-06-29
Methods for forming fan-out package structure
Grant 9,691,726 - Cheng , et al. June 27, 2
2017-06-27
Conductive External Connector Structure and Method of Forming
App 20170141059 - Shih; Meng-Fu ;   et al.
2017-05-18
Integrated circuit structure having dies with connectors
Grant 9,653,423 - Lin , et al. May 16, 2
2017-05-16
Pillar Design for Conductive Bump
App 20170084571 - Hsieh; Cheng-Chieh ;   et al.
2017-03-23
Structure and formation method for chip package
Grant 9,595,510 - Hung , et al. March 14, 2
2017-03-14
Rotary dynamic simulation device and audiovisual apparatus using the same
Grant 9,511,299 - Lai , et al. December 6, 2
2016-12-06
Packaging structures and methods with a metal pillar
Grant 9,508,666 - Yu , et al. November 29, 2
2016-11-29
Pillar design for conductive bump
Grant 9,496,235 - Hsieh , et al. November 15, 2
2016-11-15
Semiconductor Devices And Method Of Forming The Same
App 20160307862 - Lin; Meng-Liang ;   et al.
2016-10-20
Non-vertical Through-via In Package
App 20160276248 - Huang; Cheng-Lin ;   et al.
2016-09-22
Metal Oxide Layered Structure And Methods Of Forming The Same
App 20160240480 - Lin; Jing-Cheng ;   et al.
2016-08-18
Method of three dimensional integrated circuit assembly
Grant 9,418,876 - Lin , et al. August 16, 2
2016-08-16
Integrated Circuit Structure Having Dies with Connectors
App 20160204076 - Lin; Jing-Cheng ;   et al.
2016-07-14
Method and apparatus for a conductive pillar structure
Grant 9,379,080 - Chang , et al. June 28, 2
2016-06-28
Self-aligning conductive bump structure and method of fabrication
Grant 9,349,701 - Huang , et al. May 24, 2
2016-05-24
Bump structures for semiconductor package
Grant 9,343,419 - Yu , et al. May 17, 2
2016-05-17
Method for forming chip-on-wafer assembly
Grant 9,312,149 - Lin , et al. April 12, 2
2016-04-12
Integrated circuit structure having dies with connectors
Grant 9,299,680 - Lin , et al. March 29, 2
2016-03-29
Bump Structural Designs To Minimize Package Defects
App 20160035687 - LIN; Jing-Cheng ;   et al.
2016-02-04
Methods For Forming Fan-out Package Structure
App 20160013147 - Cheng; Ming-Da ;   et al.
2016-01-14
Fan-Out Package and Methods of Forming Thereof
App 20160005702 - Shih; Wan-Ting ;   et al.
2016-01-07
Bump structural designs to minimize package defects
Grant 9,159,589 - Lin , et al. October 13, 2
2015-10-13
Solder bump for ball grid array
Grant 9,159,687 - Chang , et al. October 13, 2
2015-10-13
Self-aligning Conductive Bump Structure And Method Of Fabrication
App 20150228604 - HUANG; Cheng-Lin ;   et al.
2015-08-13
Copper bump structures having sidewall protection layers
Grant 9,093,314 - Lin , et al. July 28, 2
2015-07-28
Semiconductor Structure Having An Air-gap Region And A Method Of Manufacturing The Same
App 20150200160 - SU; Shu-Hui ;   et al.
2015-07-16
Method and Apparatus for a Conductive Pillar Structure
App 20150187724 - Chang; Jung-Hua ;   et al.
2015-07-02
Integrated circuit structure having dies with connectors
Grant 9,041,225 - Lin , et al. May 26, 2
2015-05-26
Self-aligning conductive bump structure and method of making the same
Grant 9,024,438 - Huang , et al. May 5, 2
2015-05-05
Copper Bump Structures Having Sidewall Protection Layers
App 20150111342 - Lin; Jing-Cheng ;   et al.
2015-04-23
Semiconductor structure having an air-gap region and a method of manufacturing the same
Grant 8,999,839 - Su , et al. April 7, 2
2015-04-07
Method and apparatus for a conductive pillar structure
Grant 8,994,171 - Chang , et al. March 31, 2
2015-03-31
Method of making a semiconductor device including barrier layers for copper interconnect
Grant 8,975,749 - Liu , et al. March 10, 2
2015-03-10
Surface metal wiring structure for an IC substrate
Grant 8,953,336 - Kao , et al. February 10, 2
2015-02-10
Copper bump structures having sidewall protection layers
Grant 8,922,004 - Lin , et al. December 30, 2
2014-12-30
Copper bump structures having sidewall protection layers
Grant 08922004 -
2014-12-30
Pillar Design for Conductive Bump
App 20140361432 - Hsieh; Cheng-Chieh ;   et al.
2014-12-11
Connector design for packaging integrated circuits
Grant 8,901,735 - Yu , et al. December 2, 2
2014-12-02
Integrated Circuit Structure Having Dies with Connectors
App 20140346672 - Lin; Jing-Cheng ;   et al.
2014-11-27
Solder Bump for Ball Grid Array
App 20140339697 - Chang; Jung-Hua ;   et al.
2014-11-20
Plating process
Grant 8,846,524 - Kao , et al. September 30, 2
2014-09-30
Method and apparatus for a conductive bump structure
Grant 8,847,389 - Chang , et al. September 30, 2
2014-09-30
Method for Forming Chip-on-Wafer Assembly
App 20140287553 - Lin; Jing-Cheng ;   et al.
2014-09-25
Integrated Circuit Structure Having Dies with Connectors
App 20140264843 - Lin; Jing-Cheng ;   et al.
2014-09-18
Method and Apparatus for a Conductive Pillar Structure
App 20140264828 - Chang; Jung-Hua ;   et al.
2014-09-18
Method and Apparatus for a Conductive Bump Structure
App 20140264838 - Chang; Jung-Hua ;   et al.
2014-09-18
Integrated circuit structure having dies with connectors
Grant 8,803,337 - Lin , et al. August 12, 2
2014-08-12
Bump Structural Designs To Minimize Package Defects
App 20140199812 - LIN; Jing-Cheng ;   et al.
2014-07-17
Packages including active dies and dummy dies and methods for forming the same
Grant 8,779,599 - Lin , et al. July 15, 2
2014-07-15
Plating process and structure
Grant 8,759,118 - Kao , et al. June 24, 2
2014-06-24
Bump Structures For Semiconductor Package
App 20140167254 - Yu; Chen-Hua ;   et al.
2014-06-19
Connector Design for Packaging Integrated Circuits
App 20140131864 - Yu; Chen-Hua ;   et al.
2014-05-15
Method Of Making A Semiconductor Device Including Barrier Layers For Copper Interconnect
App 20140127898 - LIU; Nai-Wei ;   et al.
2014-05-08
Bump structural designs to minimize package defects
Grant 8,698,308 - Lin , et al. April 15, 2
2014-04-15
Connector design for packaging integrated circuits
Grant 8,664,760 - Yu , et al. March 4, 2
2014-03-04
Barrier layers for copper interconnect
Grant 8,653,664 - Liu , et al. February 18, 2
2014-02-18
Solder Bump For Ball Grid Array
App 20140035135 - Chang; Jung-Hua ;   et al.
2014-02-06
Packaging Structures and Methods with a Metal Pillar
App 20140038405 - Yu; Chen-Hua ;   et al.
2014-02-06
Methods for via structure with improved reliability
Grant 8,629,058 - Shue , et al. January 14, 2
2014-01-14
3D IC packaging structures and methods with a metal pillar
Grant 8,610,285 - Yu , et al. December 17, 2
2013-12-17
Plating Process and Structure
App 20130330921 - Kao; Chin-Fu ;   et al.
2013-12-12
Semiconductor Structure Having An Air-gap Region And A Method Of Manufacturing The Same
App 20130252144 - SU; Shu-Hui ;   et al.
2013-09-26
Plating process and structure
Grant 8,536,573 - Kao , et al. September 17, 2
2013-09-17
Surface Metal Wiring Structure For An Ic Substrate
App 20130233601 - KAO; Chin-Fu ;   et al.
2013-09-12
Bump Structural Designs To Minimize Package Defects
App 20130193593 - LIN; Jing-Cheng ;   et al.
2013-08-01
Plating Process and Structure
App 20130140563 - Kao; Chin-Fu ;   et al.
2013-06-06
Semiconductor structure having an air-gap region and a method of manufacturing the same
Grant 8,456,009 - Su , et al. June 4, 2
2013-06-04
Method for Forming Chip-on-Wafer Assembly
App 20130119552 - Lin; Jing-Cheng ;   et al.
2013-05-16
Plating Process and Structure
App 20130119382 - Kao; Chin-Fu ;   et al.
2013-05-16
Reducing resistivity in interconnect structures of integrated circuits
Grant 8,426,307 - Huang April 23, 2
2013-04-23
Method of Three Dimensional Integrated Circuit Assembly
App 20130056865 - Lin; Jing-Cheng ;   et al.
2013-03-07
Self-aligning Conductive Bump Structure And Method Of Making The Same
App 20130026620 - HUANG; Cheng-Lin ;   et al.
2013-01-31
Pillar Design for Conductive Bump
App 20130020698 - Hsieh; Cheng-Chieh ;   et al.
2013-01-24
Methods for Via Structure with Improved Reliability
App 20120322261 - Shue; Shau-Lin ;   et al.
2012-12-20
Connector Design for Packaging Integrated Circuits
App 20120306073 - Yu; Chen-Hua ;   et al.
2012-12-06
Packaging Structures and Methods
App 20120306080 - Yu; Chen-Hua ;   et al.
2012-12-06
Partial air gap formation for providing interconnect isolation in integrated circuits
Grant 8,304,906 - Huang , et al. November 6, 2
2012-11-06
Via structure with improved reliability
Grant 8,264,086 - Shue , et al. September 11, 2
2012-09-11
In situ Cu seed layer formation for improving sidewall coverage
Grant 8,252,690 - Su , et al. August 28, 2
2012-08-28
Copper Bump Structures Having Sidewall Protection Layers
App 20110304042 - Lin; Jing-Cheng ;   et al.
2011-12-15
Partial Air Gap Formation For Providing Interconnect Isolation In Integrated Circuits
App 20110291281 - Huang; Cheng-Lin ;   et al.
2011-12-01
Method for forming composite barrier layer
Grant 8,034,709 - Huang , et al. October 11, 2
2011-10-11
Semiconductor Structure Having An Air-gap Region And A Method Of Manufacturing The Same
App 20110198757 - SU; Shu-Hui ;   et al.
2011-08-18
Reducing Resistivity in Interconnect Structures of Integrated Circuits
App 20110171826 - Huang; Cheng-Lin
2011-07-14
Reducing resistivity in interconnect structures of integrated circuits
Grant 7,956,465 - Huang June 7, 2
2011-06-07
Reducing resistivity in interconnect structures of integrated circuits
Grant 7,919,862 - Huang April 5, 2
2011-04-05
Barrier Layers For Copper Interconnect
App 20110006429 - LIU; Nai-Wei ;   et al.
2011-01-13
Reducing Resistivity in Interconnect Structures of Integrated Circuits
App 20100171220 - Huang; Cheng-Lin
2010-07-08
Multi-step Cu seed layer formation for improving sidewall coverage
Grant 7,704,886 - Su , et al. April 27, 2
2010-04-27
Cleaning processes in the formation of integrated circuit interconnect structures
Grant 7,700,479 - Huang , et al. April 20, 2
2010-04-20
Reducing resistivity in interconnect structures by forming an inter-layer
Grant 7,612,451 - Shih , et al. November 3, 2
2009-11-03
Method for Improving the Reliability of Low-k Dielectric Materials
App 20090258487 - Lin; Keng-Chu ;   et al.
2009-10-15
In Situ Cu Seed Layer Formation for Improving Sidewall Coverage
App 20090209106 - Su; Li-Lin ;   et al.
2009-08-20
Multi-Step Cu Seed Layer Formation for Improving Sidewall Coverage
App 20090209098 - Su; Li-Lin ;   et al.
2009-08-20
Method for forming composite barrier layer
App 20090047780 - Huang; Cheng-Lin ;   et al.
2009-02-19
Composite barrier layer
Grant 7,453,149 - Huang , et al. November 18, 2
2008-11-18
Cleaning processes in the formation of integrated circuit interconnect structures
App 20080124919 - Huang; Cheng-Lin ;   et al.
2008-05-29
Micro-etching method to replicate alignment marks for semiconductor wafer photolithography
Grant 7,338,909 - Lin , et al. March 4, 2
2008-03-04
Reducing resistivity in interconnect structures by forming an inter-layer
App 20080012133 - Shih; Chih-Chao ;   et al.
2008-01-17
Reducing resistivity in interconnect structures of integrated circuits
App 20070257369 - Huang; Cheng-Lin
2007-11-08
High performance metallization cap layer
Grant 7,253,501 - Lee , et al. August 7, 2
2007-08-07
Via structure with improved reliability
App 20070126121 - Shue; Shau-Lin ;   et al.
2007-06-07
Barrier-less integration with copper alloy
Grant 7,215,024 - Lin , et al. May 8, 2
2007-05-08
Barrier structure for semiconductor devices
Grant 7,193,327 - Yu , et al. March 20, 2
2007-03-20
Barrier layer and fabrication method thereof
Grant 7,179,759 - Huang , et al. February 20, 2
2007-02-20
Via in semiconductor device
App 20070035026 - Su; Yi-Nien ;   et al.
2007-02-15
Oblique Recess For Interconnecting Conductors In A Semiconductor Device
App 20060244151 - YU; CHEN-HUA ;   et al.
2006-11-02
Barrier structure for semiconductor devices
App 20060163746 - Yu; Chen-Hua ;   et al.
2006-07-27
Barrier metal re-distribution process for resistivity reduction
Grant 7,071,095 - Huang , et al. July 4, 2
2006-07-04
Method for simultaneous degas and baking in copper damascene process
Grant 7,030,023 - Pan , et al. April 18, 2
2006-04-18
Barrier layer and fabrication method thereof
App 20060068604 - Huang; Cheng-Lin ;   et al.
2006-03-30
Composite barrier layer
App 20060027925 - Huang; Cheng-Lin ;   et al.
2006-02-09
High performance metallization cap layer
App 20060027922 - Lee; Hsien-Ming ;   et al.
2006-02-09
Micro-etching method to replicate alignment marks for semiconductor wafer photolithography
App 20050282396 - Lin, Yu-Liang ;   et al.
2005-12-22
Barrier free copper interconnect by multi-layer copper seed
App 20050263902 - Lin, Jing-Cheng ;   et al.
2005-12-01
Barrier metal re-distribution process for resistivity reduction
App 20050260851 - Huang, Cheng-Lin ;   et al.
2005-11-24
Method for high kinetic energy plasma barrier deposition
Grant 6,949,472 - Huang , et al. September 27, 2
2005-09-27
Barrier free copper interconnect by multi-layer copper seed
Grant 6,943,111 - Lin , et al. September 13, 2
2005-09-13
Pre-clean chamber with wafer heating apparatus and method of use
App 20050189075 - Pan, Shing-Chyang ;   et al.
2005-09-01
Method for simultaneous degas and baking in copper damascene process
App 20050054202 - Pan, Shing-Chyang ;   et al.
2005-03-10
Barrier-less integration with copper alloy
App 20050029665 - Lin, Jing-Cheng ;   et al.
2005-02-10
Method of barrier-less integration with copper alloy
Grant 6,806,192 - Lin , et al. October 19, 2
2004-10-19
Barrier free copper interconnect by multi-layer copper seed
App 20040157431 - Lin, Jing-Cheng ;   et al.
2004-08-12
Method of barrier-less integration with copper alloy
App 20040147104 - Lin, Jing-Cheng ;   et al.
2004-07-29
Method of improving a barrier layer in a via or contact opening
App 20040127014 - Huang, Cheng-Lin ;   et al.
2004-07-01
Barrier-free copper interconnect
Grant 6,706,629 - Lin , et al. March 16, 2
2004-03-16

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