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name:-0.020965099334717
name:-0.0016851425170898
HU; Chu-Wei Patent Filings

HU; Chu-Wei

Patent Applications and Registrations

Patent applications and USPTO patent grants for HU; Chu-Wei.The latest application filed is for "semiconductor package".

Company Profile
1.16.14
  • HU; Chu-Wei - Hsinchu City TW
  • Hu; Chu-Wei - Hsinchu TW
  • Hu; Chu-Wei - Zhubei TW
  • HU; Chu-Wei - Zhubei City TW
  • Hu; Chu-Wei - Hsinchu County N/A TW
  • Hu; Chu-Wei - Shin-Chu N/A TW
  • Hu; Chu-Wei - Taichung TW
  • Hu, Chu-Wei - Shin-Chu City TW
  • Hu; Chu-Wei - Hsin-Chu TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor Package
App 20220246591 - LU; Tien-Yu ;   et al.
2022-08-04
Semiconductor package
Grant 11,342,316 - Lu , et al. May 24, 2
2022-05-24
Semiconductor Package
App 20210225822 - LU; Tien-Yu ;   et al.
2021-07-22
Semiconductor device capable of high-voltage operation
Grant 10,418,480 - Hu , et al. Sept
2019-09-17
Integrated circuits and fabrication methods thereof
Grant 9,793,337 - Chung , et al. October 17, 2
2017-10-17
Semiconductor Device Capable Of High-voltage Operation
App 20170263761 - HU; Chu-Wei ;   et al.
2017-09-14
Integrated circuits and fabrication methods thereof
Grant 9,508,786 - Chung , et al. November 29, 2
2016-11-29
Integrated Circuits And Fabrication Methods Thereof
App 20160276338 - CHUNG; Yuan-Fu ;   et al.
2016-09-22
Integrated circuits and fabrication methods thereof
Grant 9,379,175 - Chung , et al. June 28, 2
2016-06-28
Integrated Circuits And Fabrication Methods Thereof
App 20160043162 - CHUNG; Yuan-Fu ;   et al.
2016-02-11
Bipolar junction transistor
Grant 9,123,558 - Fan , et al. September 1, 2
2015-09-01
Integrated Circuits And Fabrication Methods Thereof
App 20150187757 - CHUNG; Yuan-Fu ;   et al.
2015-07-02
Photoresist mask-free oxide define region (ODR)
Grant 8,932,937 - Lee , et al. January 13, 2
2015-01-13
Bipolar Junction Transistor
App 20120319243 - Fan; Sheng-Hung ;   et al.
2012-12-20
Method to prevent passivation layer peeling in a solder bump formation process
Grant 6,951,803 - Tzeng , et al. October 4, 2
2005-10-04
Method To Prevent Passivation Layer Peeling In A Solder Bump Formation Process
App 20050191836 - Tzeng, Kai ;   et al.
2005-09-01
Self aligned channel implant, elevated S/D process by gate electrode damascene
Grant 6,790,756 - Hu , et al. September 14, 2
2004-09-14
Sacrificial feature for corrosion prevention during CMP
Grant 6,787,470 - Hu , et al. September 7, 2
2004-09-07
Microelectronic device with a redistribution layer having a step shaped portion and method of making the same
App 20040004284 - Lee, Chu-Sheng ;   et al.
2004-01-08
Sacrificial feature for corrosion prevention during CMP
App 20030216047 - Hu, Chu-Wei ;   et al.
2003-11-20
Photoresist mask-free oxide define region (ODR)
App 20030214013 - Lee, Chu-Sheng ;   et al.
2003-11-20
Novel self aligned channel implant, elevated S/D process by gate electrode damascene
App 20030170957 - Hu, Chu-Wei ;   et al.
2003-09-11
Novel self aligned channel implant, elevated S/D process by gate electrode damascene
App 20020182815 - Hu, Chu-Wei ;   et al.
2002-12-05
Novel self aligned channel implant, elevated S/D process by gate electrode damascene
App 20020182814 - Hu, Chu-Wei ;   et al.
2002-12-05
Method of forming an aluminum protection guard structure for a copper metal structure
Grant 6,444,544 - Hu , et al. September 3, 2
2002-09-03
Self aligned channel implant, elevated S/D process by gate electrode damascene
Grant 6,287,926 - Hu , et al. September 11, 2
2001-09-11
Dual damascene process flow for a deep sub-micron technology
Grant 6,211,069 - Hu , et al. April 3, 2
2001-04-03
Formation of a thin oxide protection layer at poly sidewall and area surface
Grant 6,074,905 - Hu , et al. June 13, 2
2000-06-13

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