Hu; Chenming

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hu; Chenming.The latest application filed is for "epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof".

Company Profile

6.155.140

Hu; Chenming - Beijing CN
Hu; Chenming - Alamo CA
Hu; Chenming - Oakland CA
HU; CHENMING - Chengdu CN
Hu; Chenming - Hsin-Chu N/A TW
Hu; Chenming - Hsinchu TW
Hu; Chenming - Almo CA
Hu; Chenming - Changhua TW
Hu, Chenming - US
Hu, Chenming - Berkeley CA
Hu; Chenming - Hercules CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dioxinoquinoline compounds, preparation method and uses thereof Grant 11,407,760 - Zhang , et al. August 9, 2	2022-08-09
Semiconductor device having semiconductor alloy layer adjacent a gate structure Grant 11,380,762 - Huang , et al. July 5, 2	2022-07-05
2-substituted pyrazole amino-4-substituted amino-5-pyrimidine formamide compound, composition, and application thereof Grant 11,344,549 - Zhang , et al. May 31, 2	2022-05-31
Epitaxial Monocrystalline Channel for Storage Transistors in 3-Dimensional Memory Structures and Methods for Formation Thereof App 20210280605 - Hu; Chenming ; et al.	2021-09-09
Three Dimensional Integrated Circuit And Fabrication Thereof App 20210202475 - HU; Chenming ; et al.	2021-07-01
Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof Grant 11,049,873 - Hu , et al. June 29, 2	2021-06-29
2-substituted Pyrazole Amino-4-substituted Amino-5-pyrimidine Formamide Compound, Composition, And Application Thereof App 20210077489 - Zhang; Qiang ; et al.	2021-03-18
Memory Circuit And Manufacturing Method Thereof App 20210028178 - YOU; Wei-Xiang ; et al.	2021-01-28
Dioxinoquinoline Compounds, Preparation Method And Uses Thereof App 20200399285 - Zhang; Qiang ; et al.	2020-12-24
Breeding Method For Improving Reproductive Performance Of Chicken Specialized Dam Line App 20200396971 - JIANG; XIAOSONG ; et al.	2020-12-24
Urea-substituted Aromatic Ring-linked Dioxinoquinoline Compounds, Preparation Method And Uses Thereof App 20200399284 - Zhang; Qiang ; et al.	2020-12-24
Semiconductor device with silicided source/drain region Grant 10,818,754 - Huang , et al. October 27, 2	2020-10-27
Epitaxial Monocrystalline Channel for Storage Transistors in 3-Dimensional Memory Structures and Methods for Formation Thereof App 20200098789 - Hu; Chenming ; et al.	2020-03-26
Devices Having A Silicon-germanium Layer App 20200044030 - HUANG; Chien-Chao ; et al.	2020-02-06
Cobalt silicidation process for substrates comprised with a silicon-germanium layer Grant 10,446,646 - Huang , et al. Oc	2019-10-15
3D transistor having a gate stack including a ferroelectric film Grant 10,374,086 - Hu	2019-08-06
Semiconductor Device With Silicided Source/drain Region App 20180197955 - HUANG; Chien-Chao ; et al.	2018-07-12
Cobalt Silicidation Process for Substrates Comprised with a Silicon-Germanium Layer App 20170271449 - Huang; Chien-Chao ; et al.	2017-09-21
3d Transistor Having A Gate Stack Including A Ferroelectric Film App 20170162702 - Hu; Chenming	2017-06-08
Cobalt silicidation process for substrates comprised with a silicon-germanium layer Grant 9,673,280 - Huang , et al. June 6, 2	2017-06-06
Cobalt silicidation process for substrates comprised with a silicon-germanium layer App 20160240372 - Huang; Chien-Chao ; et al.	2016-08-18
Tunneling transistor suitable for low voltage operation Grant 9,117,893 - Hu , et al. August 25, 2	2015-08-25
Doping of semiconductor fin devices Grant 8,790,970 - Yeo , et al. July 29, 2	2014-07-29
Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same Grant 8,759,185 - Wang , et al. June 24, 2	2014-06-24
Relaxed silicon germanium substrate with low defect density Grant 8,564,018 - Lin , et al. October 22, 2	2013-10-22
Immersion fluid for immersion lithography, and method of performing immersion lithography Grant 8,488,102 - Yeo , et al. July 16, 2	2013-07-16
Tunneling transistor suitable for low voltage operation Grant 8,384,122 - Hu , et al. February 26, 2	2013-02-26
Method for dicing semiconductor wafers Grant 8,288,842 - Lee , et al. October 16, 2	2012-10-16
Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same App 20120083076 - Wang; Chih-Hao ; et al.	2012-04-05
Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same Grant 8,097,924 - Wang , et al. January 17, 2	2012-01-17
High performance CMOS devices and methods for making same Grant 8,067,280 - Wang , et al. November 29, 2	2011-11-29
Strained channel transistor structure with lattice-mismatched zone and fabrication method thereof Grant 8,062,946 - Yeo , et al. November 22, 2	2011-11-22
Doping of semiconductor fin devices Grant 8,053,839 - Yeo , et al. November 8, 2	2011-11-08
Method for fabricating a body contact in a finfet structure and a device including the same Grant 7,943,986 - Yang , et al. May 17, 2	2011-05-17
Strained silicon-on-insulator transistors with mesa isolation Grant 7,892,901 - Yeo , et al. February 22, 2	2011-02-22
Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors Grant 7,888,201 - Yeo , et al. February 15, 2	2011-02-15
Semiconductor structure having selective silicide-induced stress and a method of producing same Grant 7,875,959 - Ke , et al. January 25, 2	2011-01-25
Multiple-gate transistors formed on bulk substrates Grant 7,863,674 - Yeo , et al. January 4, 2	2011-01-04
Methods and structures for planar and multiple-gate transistors formed on SOI Grant 7,851,276 - Yang , et al. December 14, 2	2010-12-14
Immersion Fluid for Immersion Lithography, and Method of Performing Immersion Lithography App 20100177289 - Yeo; Yee-Chia ; et al.	2010-07-15
Doping of Semiconductor Fin Devices App 20100176424 - Yeo; Yee-Chia ; et al.	2010-07-15
Capacitor that includes high permittivity capacitor dielectric Grant 7,745,279 - Yeo , et al. June 29, 2	2010-06-29
Immersion fluid for immersion lithography, and method of performing immersion lithography Grant 7,700,267 - Yeo , et al. April 20, 2	2010-04-20
Doping of semiconductor fin devices Grant 7,701,008 - Yeo , et al. April 20, 2	2010-04-20
Aluminum-based interconnection in bond pad layer Grant 7,652,378 - Tseng , et al. January 26, 2	2010-01-26
Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit Grant 7,646,068 - Ko , et al. January 12, 2	2010-01-12
Gate electrode for a semiconductor fin device Grant 7,635,632 - Yeo , et al. December 22, 2	2009-12-22
Method of fabricating a non-floating body device with enhanced performance Grant 7,625,806 - Tseng , et al. December 1, 2	2009-12-01
Lithography apparatus for manufacture of integrated circuits Grant 7,579,135 - Yeo , et al. August 25, 2	2009-08-25
Method Of Fabricating A Non-floating Body Device With Enhanced Performance App 20090155965 - Tseng; Horng-Huei ; et al.	2009-06-18
Method of fabricating a non-floating body device with enhanced performance Grant 7,514,730 - Tseng , et al. April 7, 2	2009-04-07
Partial replacement silicide gate Grant 7,498,641 - Wang , et al. March 3, 2	2009-03-03
Semiconductor structure having a strained region and a method of fabricating same Grant 7,495,267 - Lee , et al. February 24, 2	2009-02-24
High Performance Cmos Devices And Methods For Making Same App 20080305590 - Wang; Chih-Hao ; et al.	2008-12-11
Method for forming a device having multiple silicide types Grant 7,459,756 - Lin , et al. December 2, 2	2008-12-02
Aluminum based conductor for via fill and interconnect Grant 7,452,805 - Wang , et al. November 18, 2	2008-11-18
Silicide/semiconductor structure and method of fabrication Grant 7,453,133 - Lee , et al. November 18, 2	2008-11-18
Semiconductor nano-wire devices and methods of fabrication Grant 7,452,778 - Chen , et al. November 18, 2	2008-11-18
Strained channel complementary field-effect transistors Grant 7,442,967 - Ko , et al. October 28, 2	2008-10-28
Semiconductor device with raised segment Grant 7,423,323 - Chen , et al. September 9, 2	2008-09-09
Aluminum-based interconnection in bond pad layer App 20080185724 - Tseng; Horng-Huei ; et al.	2008-08-07
High performance semiconductor devices fabricated with strain-induced processes and methods for making same Grant 7,394,136 - Ke , et al. July 1, 2	2008-07-01
Relaxed Silicon Germanium Substrate With Low Defect Density App 20080142842 - LIN; Chun Chich ; et al.	2008-06-19
SOI chip with recess-resistant buried insulator and method of manufacturing the same Grant 7,372,107 - Yeo , et al. May 13, 2	2008-05-13
Relaxed silicon germanium substrate with low defect density Grant 7,357,838 - Lin , et al. April 15, 2	2008-04-15
Method of forming a capacitor that includes forming a bottom electrode in a strained silicon layer Grant 7,354,843 - Yeo , et al. April 8, 2	2008-04-08
Methods of forming semiconductor devices with high-k gate dielectric Grant 7,354,830 - Lin , et al. April 8, 2	2008-04-08
Strained silicon MOS devices Grant 7,342,289 - Huang , et al. March 11, 2	2008-03-11
Transistor with a strained region and method of manufacture Grant 7,335,929 - Lin , et al. February 26, 2	2008-02-26
Semiconductor-on-insulator chip with<100>-oriented transistors Grant 7,319,258 - Yang , et al. January 15, 2	2008-01-15
Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance Grant 7,312,136 - Huang , et al. December 25, 2	2007-12-25
Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors Grant 7,301,206 - Yeo , et al. November 27, 2	2007-11-27
Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors App 20070264762 - Yeo; Yee-Chia ; et al.	2007-11-15
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling Grant 7,294,937 - Su , et al. November 13, 2	2007-11-13
Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof Grant 7,279,756 - Wang , et al. October 9, 2	2007-10-09
Method for Fabricating a Body Contact in a Finfet Structure and a Device Including the Same App 20070228372 - Yang; Kuo-Nan ; et al.	2007-10-04
Alluminum base conductor for via fill interconnect App 20070218686 - Wang; Chao-Hsiung ; et al.	2007-09-20
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors Grant 7,268,024 - Yeo , et al. September 11, 2	2007-09-11
Interconnect with composite layers and method for fabricating the same Grant 7,265,447 - Yu , et al. September 4, 2	2007-09-04
Contacts to semiconductor fin devices Grant 7,262,086 - Yeo , et al. August 28, 2	2007-08-28
Strained silicon-on-insulator transistors with mesa isolation App 20070190702 - Yeo; Yee-Chia ; et al.	2007-08-16
Cobalt silicidation process for substrates comprised with a silicon-germanium layer App 20070164369 - Huang; Chien-Chao ; et al.	2007-07-19
Method for fabricating a body contact in a Finfet structure and a device including the same Grant 7,244,640 - Yang , et al. July 17, 2	2007-07-17
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement Grant 7,238,989 - Yeo , et al. July 3, 2	2007-07-03
Methods and Structures for Planar and Multiple-Gate Transistors Formed on SOI App 20070134860 - Yang; Fu-Liang ; et al.	2007-06-14
Method for dicing semiconductor wafers App 20070117352 - Lee; Hsin-Hui ; et al.	2007-05-24
Gate electrode for a semiconductor fin device App 20070111454 - Yeo; Yee-Chia ; et al.	2007-05-17
Multiple-gate transistors formed on bulk substrates App 20070102763 - Yeo; Yee-Chia ; et al.	2007-05-10
CMOS inverters configured using multiple-gate transistors Grant 7,214,991 - Yeo , et al. May 8, 2	2007-05-08
CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof Grant 7,208,815 - Chen , et al. April 24, 2	2007-04-24
Strained silicon structure Grant 7,208,754 - Ge , et al. April 24, 2	2007-04-24
Cobalt silicidation process for substrates with a silicon--germanium layer Grant 7,202,122 - Huang , et al. April 10, 2	2007-04-10
Necked Finfet device App 20070063261 - CHEN; Haur-Ywh ; et al.	2007-03-22
High performance tunneling-biased MOSFET and a process for its manufacture Grant 7,187,000 - Yang , et al. March 6, 2	2007-03-06
Semiconductor structure having selective silicide-induced stress and a method of producing same App 20070045849 - Ke; Chung-Hu ; et al.	2007-03-01
Heterostructure resistor and method of forming the same Grant 7,183,593 - Yeo , et al. February 27, 2	2007-02-27
Method for dicing semiconductor wafers Grant 7,183,137 - Lee , et al. February 27, 2	2007-02-27
Methods and structures for planar and multiple-gate transistors formed on SOI Grant 7,180,134 - Yang , et al. February 20, 2	2007-02-20
Gate electrode for a semiconductor fin device Grant 7,176,092 - Yeo , et al. February 13, 2	2007-02-13
Multiple-gate transistors formed on bulk substrates Grant 7,172,943 - Yeo , et al. February 6, 2	2007-02-06
Self-aligned contact for silicon-on-insulator devices Grant 7,173,305 - Yang , et al. February 6, 2	2007-02-06
Hybrid fractional-bit systems Grant 7,167,109 - Hu , et al. January 23, 2	2007-01-23
Strained silicon-on-insulator transistors with mesa isolation Grant 7,157,774 - Yeo , et al. January 2, 2	2007-01-02
A Method For Forming A Device Having Multiple Silicide Types App 20060286740 - LIN; Chun-Chieh ; et al.	2006-12-21
Dual work function CMOS gate technology based on metal interdiffusion Grant 7,141,858 - Polishchuk , et al. November 28, 2	2006-11-28
Silicon-on-insulator ULSI devices with multiple silicon film thicknesses Grant 7,141,459 - Yang , et al. November 28, 2	2006-11-28
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling App 20060261490 - Su; Chao-Yuan ; et al.	2006-11-23
Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit App 20060255365 - Ko; Chih-Hsin ; et al.	2006-11-16
Contacts to semiconductor fin devices App 20060244066 - Yeo; Yee-Chia ; et al.	2006-11-02
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling Grant 7,126,225 - Su , et al. October 24, 2	2006-10-24
Doping of semiconductor fin devices App 20060234431 - Yeo; Yee-Chia ; et al.	2006-10-19
Self-aligned contact for silicon-on-insulator devices App 20060234438 - Yang; Fu-Liang ; et al.	2006-10-19
Method of fabricating a necked FINFET device Grant 7,122,412 - Chen , et al. October 17, 2	2006-10-17
Resistor with reduced leakage App 20060226487 - Yeo; Yee-Chia ; et al.	2006-10-12
Hybrid Fractional-bit Systems App 20060227021 - HU; Chenming ; et al.	2006-10-12
Doping of semiconductor fin devices App 20060220133 - Yeo; Yee-Chia ; et al.	2006-10-05
Method for forming a device having multiple silicide types Grant 7,112,483 - Lin , et al. September 26, 2	2006-09-26
Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit Grant 7,112,495 - Ko , et al. September 26, 2	2006-09-26
Semiconductor structure having a strained region and a method of fabricating same App 20060208336 - Lee; Wen-Chin ; et al.	2006-09-21
High performance tunneling-biased MOSFET and a process for its manufacture App 20060208316 - Yang; Kuo-Nan ; et al.	2006-09-21
Copper wiring with high temperature superconductor (HTS) layer Grant 7,105,928 - Yu , et al. September 12, 2	2006-09-12
Contacts to semiconductor fin devices Grant 7,105,894 - Yeo , et al. September 12, 2	2006-09-12
Strained channel complementary field-effect transistors and methods of manufacture Grant 7,101,742 - Ko , et al. September 5, 2	2006-09-05
Thermal anneal process for strained-Si devices Grant 7,098,119 - Ke , et al. August 29, 2	2006-08-29
Strained channel complementary field-effect transistors and methods of manufacture App 20060189056 - Ko; Chih-Hsin ; et al.	2006-08-24
Methods of forming semiconductor devices with high-k gate dielectric App 20060177997 - Lin; Chun-Chieh ; et al.	2006-08-10
Accumulation mode multiple gate transistor App 20060170053 - Yeo; Yee-Chia ; et al.	2006-08-03
Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials Grant 7,081,395 - Chi , et al. July 25, 2	2006-07-25
Tamper-Proof Content-Playback System Offering Excellent Copyright Protection App 20060159424 - HU; Chenming ; et al.	2006-07-20
Tamper-Proof Content-Playback System Offering Excellent Copyright Protection App 20060158737 - HU; Chenming ; et al.	2006-07-20
Tamper-Proof Content-Playback System Offering Excellent Copyright Protection App 20060159423 - ZHANG; Guobiao ; et al.	2006-07-20
Doping of semiconductor fin devices Grant 7,074,656 - Yeo , et al. July 11, 2	2006-07-11
Resistor with reduced leakage Grant 7,071,052 - Yeo , et al. July 4, 2	2006-07-04
Novel CMOS device App 20060138557 - Huang; Chien-Chao ; et al.	2006-06-29
Capacitor that includes high permittivity capacitor dielectric App 20060124965 - Yeo; Yee-Chia ; et al.	2006-06-15
Method for forming devices with multiple spacer widths Grant 7,057,237 - Wang , et al. June 6, 2	2006-06-06
High performance CMOS devices and methods for making same App 20060113591 - Wan; Chih-Hao ; et al.	2006-06-01
Strained channel transistor and methods of manufacture Grant 7,052,964 - Yeo , et al. May 30, 2	2006-05-30
Semiconductor structure having a strained region and a method of fabricating same Grant 7,045,836 - Lee , et al. May 16, 2	2006-05-16
Semiconductor device with high-k gate dielectric Grant 7,045,847 - Lin , et al. May 16, 2	2006-05-16
Method of manufacturing an integrated circuit including capacitor with high permittivity capacitor dielectric Grant 7,037,772 - Yeo , et al. May 2, 2	2006-05-02
Transistor with a strained region and method of manufacture App 20060081875 - Lin; Chun-Chieh ; et al.	2006-04-20
Method for fabricating a body contact in a finfet structure and a device including the same App 20060084211 - Yang; Kuo-Nan ; et al.	2006-04-20
Strained channel on insulator device Grant 7,029,994 - Ge , et al. April 18, 2	2006-04-18
CMOS device Grant 7,022,561 - Huang , et al. April 4, 2	2006-04-04
CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof App 20060049460 - Chen; Hung-Wei ; et al.	2006-03-09
Interconnect with composite barrier layers and method for fabricating the same App 20060027932 - Yu; Chen-Hua ; et al.	2006-02-09
Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof App 20060017112 - Wang; Chih-Hao ; et al.	2006-01-26
SOI chip with mesa isolation and recess resistant regions Grant 6,979,867 - Yeo , et al. December 27, 2	2005-12-27
SOI chip with recess-resistant buried insulator and method of manufacturing the same App 20050275024 - Yeo, Yee-Chia ; et al.	2005-12-15
Semiconductor nano-wire devices and methods of fabrication App 20050275010 - Chen, Hung-Wei ; et al.	2005-12-15
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement App 20050272188 - Yeo, Yee-Chia ; et al.	2005-12-08
Partial replacement silicide gate App 20050263830 - Wang, Chih-Hao ; et al.	2005-12-01
High performance semiconductor devices fabricated with strain-induced processes and methods for making same App 20050263828 - Ke, Chung-Hu ; et al.	2005-12-01
Thermal anneal process for strained-Si devices App 20050253166 - Ke, Chung-Hu ; et al.	2005-11-17
Method of fabricating a necked finfet device App 20050253193 - Chen, Haur-Ywh ; et al.	2005-11-17
Capacitor that includes high permittivity capacitor dielectric App 20050248906 - Yeo, Yee-Chia ; et al.	2005-11-10
Interconnect with composite barrier layers and method for fabricating the same Grant 6,958,291 - Yu , et al. October 25, 2	2005-10-25
Strained channel on insulator device App 20050233552 - Ke, Chung-Hu ; et al.	2005-10-20
Gate electrode for a semiconductor fin device App 20050233525 - Yeo, Yee-Chia ; et al.	2005-10-20
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement Grant 6,955,952 - Yeo , et al. October 18, 2	2005-10-18
High performance semiconductor devices fabricated with strain-induced processes and methods for making same Grant 6,949,443 - Ke , et al. September 27, 2	2005-09-27
Suppression of MOSFET gate leakage current Grant 6,949,769 - Hu , et al. September 27, 2	2005-09-27
SOI chip with recess-resistant buried insulator and method of manufacturing the same Grant 6,949,451 - Yeo , et al. September 27, 2	2005-09-27
Capacitor with enhanced performance and method of manufacture App 20050208717 - Yeo, Yee-Chia ; et al.	2005-09-22
Strained silicon structure App 20050194658 - Ke, Chung-Hu ; et al.	2005-09-08
Capacitor with enhanced performance and method of manufacture Grant 6,940,705 - Yeo , et al. September 6, 2	2005-09-06
Capacitor that includes high permittivity capacitor dielectric Grant 6,936,881 - Yeo , et al. August 30, 2	2005-08-30
Strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof App 20050170594 - Yeo, Yee-Chia ; et al.	2005-08-04
Methods and structures for planar and multiple-gate transistors formed on SOI App 20050167750 - Yang, Fu-Liang ; et al.	2005-08-04
Strained-channel transistor structure with lattice-mismatched zone Grant 6,921,913 - Yeo , et al. July 26, 2	2005-07-26
Strained channel transistor and methods of manufacture App 20050156274 - Yeo, Yee-Chia ; et al.	2005-07-21
Device having multiple silicide types and a method for its fabrication App 20050156208 - Lin, Chun-Chieh ; et al.	2005-07-21
Method of fabricating a non-floating body device with enhanced performance App 20050156156 - Tseng, Horng-Huei ; et al.	2005-07-21
Semiconductor device with raised segment App 20050156248 - Chen, Hao-Yu ; et al.	2005-07-21
Relaxed silicon germanium substrate with low defect density App 20050158971 - Lin, Chun Chich ; et al.	2005-07-21
Devices with high-k gate dielectric App 20050145956 - Wang, Chih-Hao ; et al.	2005-07-07
Improved Cobalt Silicidation Process for Substrates with a Silicon Germanium Layer App 20050133817 - Huang, Chien-Chao ; et al.	2005-06-23
Heterostructure resistor and method of forming the same App 20050127400 - Yeo, Yee-Chia ; et al.	2005-06-16
Semiconductor chip with gate dielectrics for high-performance and low-leakage applications Grant 6,906,398 - Yeo , et al. June 14, 2	2005-06-14
Semiconductor nano-rod devices App 20050121706 - Chen, Hao-Yu ; et al.	2005-06-09
Strained silicon structure Grant 6,902,965 - Ge , et al. June 7, 2	2005-06-07
Method for dicing semiconductor wafers App 20050118790 - Lee, Hsin-Hui ; et al.	2005-06-02
Complementary field-effect transistors and methods of manufacture App 20050116360 - Huang, Chien-Chao ; et al.	2005-06-02
Strained channel on insulator device Grant 6,900,502 - Ge , et al. May 31, 2	2005-05-31
SOI chip with mesa isolation and recess resistant regions App 20050101111 - Yeo, Yee-Chia ; et al.	2005-05-12
Semiconductor-on-insulator chip with<100>-oriented transistors App 20050093105 - Yang, Fu-Liang ; et al.	2005-05-05
Strained Silicon Structure App 20050093018 - Ge, Chung-Hu ; et al.	2005-05-05
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors App 20050093067 - Yeo, Yee-Chia ; et al.	2005-05-05
Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same App 20050093084 - Wang, Chih-Hao ; et al.	2005-05-05
Strained-channel transistor and methods of manufacture Grant 6,882,025 - Yeo , et al. April 19, 2	2005-04-19
High performance semiconductor devices fabricated with strain-induced processes and methods for making same App 20050079677 - Ke, Chung-Hu ; et al.	2005-04-14
Copper wiring with high temperature superconductor (HTS) layer App 20050077627 - Yu, Chen-Hua ; et al.	2005-04-14
Relaxed silicon germanium substrate with low defect density Grant 6,878,610 - Lin , et al. April 12, 2	2005-04-12
Semiconductor device with raised segment Grant 6,872,606 - Chen , et al. March 29, 2	2005-03-29
Dummy pattern for silicide gate electrode App 20050056881 - Yeo, Yee-Chia ; et al.	2005-03-17
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors Grant 6,867,433 - Yeo , et al. March 15, 2	2005-03-15
Method for forming devices with multiple spacer widths App 20050051866 - Wang, Howard Chih Hao ; et al.	2005-03-10
Interconnect with composite barrier layers and method for fabricating the same App 20050054191 - Yu, Chen-Hua ; et al.	2005-03-10
CMOS SRAM cell configured using multiple-gate transistors Grant 6,864,519 - Yeo , et al. March 8, 2	2005-03-08
SOI chip with mesa isolation and recess resistant regions Grant 6,864,149 - Yeo , et al. March 8, 2	2005-03-08
Device having multiple silicide types and a method for its fabrication App 20050045965 - Lin, Chun-Chieh ; et al.	2005-03-03
Silicide/semiconductor structure and method of fabrication App 20050045969 - Lee, Wen-Chin ; et al.	2005-03-03
Ultra-thin body transistor with recessed silicide contacts App 20050045949 - Lin, Chun-Chieh ; et al.	2005-03-03
Suppression of MOSFET gate leakage current App 20050040404 - Hu, Chenming ; et al.	2005-02-24
Resistor with reduced leakage App 20050040493 - Yeo, Yee-Chia ; et al.	2005-02-24
Semiconductor device with high-k gate dielectric App 20050035345 - Lin, Chun-Chieh ; et al.	2005-02-17
Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit App 20050035409 - Ko, Chih-Hsin ; et al.	2005-02-17
Lithography apparatus for manufacture of integrated circuits App 20050036184 - Yeo, Yee-Chia ; et al.	2005-02-17
Immersion fluid for immersion Lithography, and method of performing immersion lithography App 20050036183 - Yeo, Yee-Chia ; et al.	2005-02-17
Multiple-gate transistors formed on bulk substrates App 20050035415 - Yeo, Yee-Chia ; et al.	2005-02-17
Strained channel complementary field-effect transistors and methods of manufacture App 20050035470 - Ko, Chih-Hsin ; et al.	2005-02-17
Semiconductor diode with reduced leakage App 20050035410 - Yeo, Yee-Chia ; et al.	2005-02-17
Structure and method of forming integrated circuits utilizing strained channel transistors App 20050035369 - Lin, Chun-Chieh ; et al.	2005-02-17
Device with low-k dielectric in close proximity thereto and its method of fabrication App 20050035455 - Hu, Chenming ; et al.	2005-02-17
Semiconductor nano-rod devices Grant 6,855,606 - Chen , et al. February 15, 2	2005-02-15
Strained-channel multiple-gate transistor Grant 6,855,990 - Yeo , et al. February 15, 2	2005-02-15
Strained silicon MOS devices App 20050032321 - Huang, Chien-Chao ; et al.	2005-02-10
Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors App 20050023633 - Yeo, Yee-Chia ; et al.	2005-02-03
Semiconductor structure having a strained region and a method of fabricating same App 20050023576 - Lee, Wen-Chin ; et al.	2005-02-03
Capacitor with improved capacitance density and method of manufacture App 20050017286 - Yeo, Yee-Chia ; et al.	2005-01-27
Capacitor with enhanced performance and method of manufacture App 20050018380 - Yeo, Yee-Chia ; et al.	2005-01-27
Non-floating body device with enhanced performance Grant 6,847,098 - Tseng , et al. January 25, 2	2005-01-25
Multiple-gate transistors with improved gate control Grant 6,844,238 - Yeo , et al. January 18, 2	2005-01-18
Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement App 20040266128 - Chen, Haur-Ywh ; et al.	2004-12-30
Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance App 20040266137 - Huang, Chien-Chao ; et al.	2004-12-30
Suppression of MOSFET gate leakage current Grant 6,830,953 - Hu , et al. December 14, 2	2004-12-14
Dual work function CMOS gate technology based on metal interdiffusion App 20040238859 - Polishchuk, Igor ; et al.	2004-12-02
Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials App 20040232513 - Chi, Min-Hwa ; et al.	2004-11-25
SOI chip with mesa isolation and recess resistant regions App 20040222463 - Yeo, Yee-Chia ; et al.	2004-11-11
Doping of semiconductor fin devices App 20040217433 - Yeo, Yee-Chia ; et al.	2004-11-04
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors App 20040217420 - Yeo, Yee-Chia ; et al.	2004-11-04
Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance Grant 6,812,116 - Huang , et al. November 2, 2	2004-11-02
Strained-channel transistor and methods of manufacture App 20040212035 - Yeo, Yee-Chia ; et al.	2004-10-28
Self-aligned contact for silicon-on-insulator devices App 20040203211 - Yang, Fu-Liang ; et al.	2004-10-14
Strained channel on insulator device App 20040195623 - Ge, Chung-Hu ; et al.	2004-10-07
Semiconductor device with raised segment App 20040197969 - Chen, Hao-Yu ; et al.	2004-10-07
Multiple-gate transistors with improved gate control App 20040198003 - Yeo, Yee-Chia ; et al.	2004-10-07
Low-voltage punch-through transient suppressor employing a dual-base structure Grant RE38,608 - Yu , et al. October 5, 2	2004-10-05
Dual work function CMOS gate technology based on metal interdiffusion Grant 6,794,234 - Polishchuk , et al. September 21, 2	2004-09-21
Silicon-on-insulator ulsi devices with multiple silicon film thicknesses App 20040180478 - Yang, Fu-Liang ; et al.	2004-09-16
SOI chip with recess-resistant buried insulator and method of manufacturing the same App 20040178447 - Yeo, Yee-Chia ; et al.	2004-09-16
Method of fabricating a salicided device using a dummy dielectric layer between the source/drain and the gate electrode App 20040175907 - Tseng, Horng-Huei ; et al.	2004-09-09
Strained-channel Transistor Structure With Lattice-mismatched Zone App 20040173815 - Yeo, Yee-Chia ; et al.	2004-09-09
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement App 20040175872 - Yeo, Yee-Chia ; et al.	2004-09-09
Contacts to semiconductor fin devices App 20040169269 - Yeo, Yee-Chia ; et al.	2004-09-02
Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement Grant 6,784,071 - Chen , et al. August 31, 2	2004-08-31
Semiconductor nano-rod devices App 20040166642 - Chen, Hao-Yu ; et al.	2004-08-26
BONDED SOI WAFER WITH <100> DEVICE LAYER AND <110> SUBSTRATE FOR PERFORMANCE IMPROVEMENT App 20040151917 - Chen, Haur-Ywh ; et al.	2004-08-05
Semiconductor chip with gate dielectrics for high-performance and low-leakage applications App 20040129995 - Yeo, Yee-Chia ; et al.	2004-07-08
Method Of Fabricating A Wafer With Strained Channel Layers For Increased Electron And Hole Mobility For Improving Device Performance App 20040115900 - Huang, Chien-Chao ; et al.	2004-06-17
CMOS inverters configured using multiple-gate transistors App 20040110331 - Yeo, Yee-Chia ; et al.	2004-06-10
Novel CMOS device App 20040104405 - Huang, Chien-Chao ; et al.	2004-06-03
Strained-channel multiple-gate transistor App 20040099903 - Yeo, Yee-Chia ; et al.	2004-05-27
CMOS SRAM cell configured using multiple-gate transistors App 20040099885 - Yeo, Yee-Chia ; et al.	2004-05-27
Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices Grant 6,720,619 - Chen , et al. April 13, 2	2004-04-13
High performance PD SOI tunneling-biased MOSFET Grant 6,674,130 - Yang , et al. January 6, 2	2004-01-06
Method of fabricating a non-floating body device with enhanced performance Grant 6,627,515 - Tseng , et al. September 30, 2	2003-09-30
Dual work function CMOS gate technology based on metal interdiffusion App 20030180994 - Polishchuk, Igor ; et al.	2003-09-25
Antifuse structure suitable for VLSI application Grant 6,603,187 - Zhang , et al. August 5, 2	2003-08-05
High performance PD SOI tunneling-biased mosfet App 20030122214 - Yang, Kuo-Nan ; et al.	2003-07-03
High performance PD SOI tunneling-biased MOSFET Grant 6,518,105 - Yang , et al. February 11, 2	2003-02-11
Method of forming a transistor with a strained channel Grant 6,492,216 - Yeo , et al. December 10, 2	2002-12-10
Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture Grant 6,413,802 - Hu , et al. July 2, 2	2002-07-02
Method of separating films from bulk substrates by plasma immersion ion implantation App 20020064924 - Cheung, Nathan W. ; et al.	2002-05-30
Method of separation films from bulk substrates by plasma immersion ion implantation Grant 6,344,404 - Cheung , et al. February 5, 2	2002-02-05
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility Grant 6,300,649 - Hu , et al. October 9, 2	2001-10-09
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility Grant 6,121,077 - Hu , et al. September 19, 2	2000-09-19
Antifuse structure suitable for VLSI application Grant 6,111,302 - Zhang , et al. August 29, 2	2000-08-29
Low-voltage punch-through transient suppressor employing a dual-base structure Grant 6,015,999 - Yu , et al. January 18, 2	2000-01-18
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility Grant 5,982,003 - Hu , et al. November 9, 1	1999-11-09
Realistic worst-case circuit simulation system and method Grant 5,790,436 - Chen , et al. August 4, 1	1998-08-04
Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation Grant 5,780,899 - Hu , et al. July 14, 1	1998-07-14
Ferroelectric nonvolatile dynamic random access memory device Grant 5,768,182 - Hu , et al. June 16, 1	1998-06-16
Electrically programmable antifuse Grant 5,670,818 - Forouhi , et al. September 23, 1	1997-09-23
ESD and hot carrier resistant integrated circuit structure Grant 5,631,485 - Wei , et al. May 20, 1	1997-05-20
Method of fabricating a self-aligned high speed MOSFET device Grant 5,599,728 - Hu , et al. February 4, 1	1997-02-04
Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation Grant 5,559,368 - Hu , et al. September 24, 1	1996-09-24
Pseudo-nonvolatile memory incorporating data refresh operation Grant 5,511,020 - Hu , et al. April 23, 1	1996-04-23
Method of forming an ESD and hot carrier resistant integrated circuit structure Grant 5,496,751 - Wei , et al. March 5, 1	1996-03-05
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility Grant 5,489,792 - Hu , et al. February 6, 1	1996-02-06
Capacitorless DRAM device on silicon-on-insulator substrate Grant 5,448,513 - Hu , et al. September 5, 1	1995-09-05
Electrically programmable antifuse and fabrication processes Grant 5,272,101 - Forouhi , et al. December 21, 1	1993-12-21
High voltage power IC process Grant 4,908,328 - Hu , et al. March 13, 1	1990-03-13
Electrically programmable memory device employing source side injection Grant 4,794,565 - Wu , et al. December 27, 1	1988-12-27
Nonvolatile memory cell Grant 4,538,246 - Wang , et al. August 27, 1	1985-08-27
Electrically erasable programmable read only memory Grant 4,366,555 - Hu December 28, 1	1982-12-28

Company Registrations

SEC

0001316320

Hu Chenming