Hsueh; Hsiu-Wen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hsueh; Hsiu-Wen.The latest application filed is for "diffusion barrier layer for conductive via to decrease contact resistance".

Company Profile

8.8.15

Hsueh; Hsiu-Wen - Taichung City TW
Hsueh; Hsiu-Wen - Taichung TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Diffusion Barrier Layer For Conductive Via To Decrease Contact Resistance App 20220310526 - Hsueh; Hsiu-Wen ; et al.	2022-09-29
Self-Aligned Scheme for Semiconductor Device and Method of Forming the Same App 20220277991 - Hsueh; Hsiu-Wen ; et al.	2022-09-01
E-fuse enhancement by underlayer layout design Grant 11,410,926 - Fu , et al. August 9, 2	2022-08-09
Diffusion barrier layer for conductive via to decrease contact resistance Grant 11,362,035 - Hsueh , et al. June 14, 2	2022-06-14
Self-aligned scheme for semiconductor device and method of forming the same Grant 11,342,222 - Hsueh , et al. May 24, 2	2022-05-24
Semiconductor Device Structure With Resistive Element App 20220130727 - HUANG; Wen-Sheh ; et al.	2022-04-28
Method for forming semiconductor device with resistive element Grant 11,217,482 - Huang , et al. January 4, 2	2022-01-04
Inter-wire Cavity For Low Capacitance App 20210335655 - Hsueh; Hsiu-Wen ; et al.	2021-10-28
Barrier Free Interface Between Beol Interconnects App 20210335663 - Hsueh; Hsiu-Wen ; et al.	2021-10-28
Diffusion Barrier Layer For Conductive Via To Decrease Contact Resistance App 20210287994 - Hsueh; Hsiu-Wen ; et al.	2021-09-16
Semiconductor Device Structure With Resistive Elements App 20210249251 - HSUEH; Hsiu-Wen ; et al.	2021-08-12
Structure and formation method of semiconductor device with resistive elements Grant 10,985,011 - Hsueh , et al. April 20, 2	2021-04-20
E-Fuse Enhancement By Underlayer Layout Design App 20210098372 - Fu; An-Jiao ; et al.	2021-04-01
Self-Aligned Scheme for Semiconductor Device and Method of Forming the Same App 20210098290 - Hsueh; Hsiu-Wen ; et al.	2021-04-01
Method For Forming Semiconductor Device With Resistive Element App 20200118876 - HUANG; Wen-Sheh ; et al.	2020-04-16
Structure and formation method of semiconductor device with resistive element Grant 10,515,852 - Huang , et al. Dec	2019-12-24
Structure And Formation Method Of Semiconductor Device With Resistive Elements App 20190139754 - HSUEH; Hsiu-Wen ; et al.	2019-05-09
Structure And Formation Method Of Semiconductor Device With Resistive Element App 20190139826 - HUANG; Wen-Sheh ; et al.	2019-05-09
Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout Grant 9,922,162 - Ho , et al. March 20, 2	2018-03-20
Resistive Capacitance Determination Method For Multiple-patterning-multiple Spacer Integrated Circuit Layout App 20160103948 - HO; Chia-Ming ; et al.	2016-04-14
Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout Grant 9,218,448 - Ho , et al. December 22, 2	2015-12-22
Resistive Capacitance Determination Method For Multiple-patterning-multiple Spacer Integrated Circuit Layout App 20150205905 - HO; Chia-Ming ; et al.	2015-07-23
Metal Oxide Thin Film Transistor And Manufacturing Method Thereof App 20120112180 - ZAN; HSIAO-WEN ; et al.	2012-05-10

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