Hsu; Yarsun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hsu; Yarsun.The latest application filed is for "multi-mode multi-parallelism data exchange method and device thereof".

Company Profile

0.11.2

Hsu; Yarsun - Jhonghe TW
Hsu; Yarsun - Jhonghe City TW
Hsu; Yarsun - Pleasantville NY
Hsu; Yarsun - Pleasanville NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Operating method and circuit for low density parity check (LDPC) decoder Grant 8,108,762 - Liu , et al. January 31, 2	2012-01-31
Multi-mode multi-parallelism data exchange method and device thereof Grant 7,719,442 - Liu , et al. May 18, 2	2010-05-18
Multi-mode Multi-parallelism Data Exchange Method And Device Thereof App 20090146849 - LIU; Chih-Hao ; et al.	2009-06-11
Operating Method Applied To Low Density Parity Check (ldpc) Decoder And Circuit Thereof App 20090037799 - LIU; Chih-Hao ; et al.	2009-02-05
Method for providing virtual atomicity in multi processor environment having access to multilevel caches Grant 6,175,899 - Baylor , et al. January 16, 2	2001-01-16
Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes Grant 6,148,375 - Baylor , et al. November 14, 2	2000-11-14
Cache coherence for lazy entry consistency in lockup-free caches Grant 6,094,709 - Baylor , et al. July 25, 2	2000-07-25
Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors Grant 5,822,763 - Baylor , et al. October 13, 1	1998-10-13
Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory Grant 5,778,437 - Baylor , et al. July 7, 1	1998-07-07
Switch queue structure for one-network parallel processor systems Grant 5,313,649 - Hsu , et al. May 17, 1	1994-05-17
Network rearrangement method and system Grant 5,287,491 - Hsu February 15, 1	1994-02-15
Single-FIFO high speed combining switch Grant 5,046,000 - Hsu September 3, 1	1991-09-03
Programmable variable-cycle clock circuit for skew-tolerant array processor architecture Grant 4,851,995 - Hsu , et al. July 25, 1	1989-07-25

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