Hsu; Shun-Liang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hsu; Shun-Liang.The latest application filed is for "lateral power mosfet with high breakdown voltage and low on-resistance".

Company Profile

0.39.20

Hsu; Shun-Liang - Hsin-Chu N/A TW
Hsu; Shun-Liang - Hsinchu TW
Hsu; Shun-Liang - Taipei TW
Hsu; Shun-Liang - Hsin Chu City TW
Hsu; Shun-Liang - Hsinchu City TW
Hsu, Shun-Liang - Taipei City TW
Hsu; Shun-Liang - Mountain-Lake Village TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method to improve bump reliability for flip chip device Grant 8,497,584 - Chen , et al. July 30, 2	2013-07-30
Lateral power MOSFET with high breakdown voltage and low on-resistance Grant 8,389,341 - Huang , et al. March 5, 2	2013-03-05
Lateral power MOSFET with high breakdown voltage and low on-resistance Grant 8,129,783 - Huang , et al. March 6, 2	2012-03-06
High voltage CMOS devices Grant 8,114,745 - Wu , et al. February 14, 2	2012-02-14
Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance App 20120003803 - Huang; Tsung-Yi ; et al.	2012-01-05
Lateral power MOSFET with high breakdown voltage and low on-resistance Grant 7,989,890 - Huang , et al. August 2, 2	2011-08-02
Isolation structure in field device Grant 7,911,022 - Wu , et al. March 22, 2	2011-03-22
High Voltage CMOS Devices App 20100203691 - Wu; Chen-Bau ; et al.	2010-08-12
High voltage CMOS devices Grant 7,719,064 - Wu , et al. May 18, 2	2010-05-18
Method and apparatus for polymer dielectric surface recovery by ion implantation Grant 7,714,414 - Yu , et al. May 11, 2	2010-05-11
Shielding structures for preventing leakages in high voltage MOS devices Grant 7,521,741 - Jong , et al. April 21, 2	2009-04-21
Semiconductor structure with high-voltage sustaining capability and fabrication method of the same Grant 7,521,342 - Wu , et al. April 21, 2	2009-04-21
Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance App 20090085101 - Huang; Tsung-Yi ; et al.	2009-04-02
High voltage semiconductor device utilizing a deep trench structure Grant 7,482,662 - Wu , et al. January 27, 2	2009-01-27
Lateral power MOSFET with high breakdown voltage and low on-resistance Grant 7,476,591 - Huang , et al. January 13, 2	2009-01-13
Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance App 20090001462 - Huang; Tsung-Yi ; et al.	2009-01-01
High Voltage CMOS Devices App 20080191291 - Wu; Chen-Bau ; et al.	2008-08-14
Integrated circuit transistor insulating region fabrication method Grant 7,384,836 - Wu , et al. June 10, 2	2008-06-10
High voltage CMOS devices Grant 7,372,104 - Wu , et al. May 13, 2	2008-05-13
Lateral power MOSFET with high breakdown voltage and low on-resistance App 20080090347 - Huang; Tsung-Yi ; et al.	2008-04-17
Semiconductor structure with high-voltage sustaining capability and fabrication method of the same App 20080085579 - Wu; Chen-Bau ; et al.	2008-04-10
Shielding structures for preventing leakages in high voltage MOS devices App 20080001189 - Jong; Yu-Chang ; et al.	2008-01-03
Semiconductor structure with high-voltage sustaining capability and fabrication method of the same Grant 7,279,767 - Wu , et al. October 9, 2	2007-10-09
High Voltage Semiconductor Device Utilizing A Deep Trench Structure App 20070187766 - Wu; Chen-Bau ; et al.	2007-08-16
High voltage CMOS devices App 20070132033 - Wu; Chen-Bau ; et al.	2007-06-14
Method of forming high voltage devices with retrograde well Grant 7,221,021 - Wu , et al. May 22, 2	2007-05-22
Integrated circuit transistor insulating region fabrication method App 20060286735 - Wu; You-Kuo ; et al.	2006-12-21
High voltage semiconductor device utilizing a deep trench structure Grant 7,129,559 - Wu , et al. October 31, 2	2006-10-31
Isolation-region configuration for integrated-circuit transistor Grant 7,122,876 - Wu , et al. October 17, 2	2006-10-17
Semiconductor structure with high-voltage sustaining capability and fabrication method of the same App 20060170060 - Wu; Chen-Bau ; et al.	2006-08-03
Isolation structure in field device App 20060157816 - Wu; You-Kuo ; et al.	2006-07-20
Programmable MOS device formed by stressing polycrystalline silicon Grant 7,079,412 - Chen , et al. July 18, 2	2006-07-18
Method and apparatus for polymer dielectric surface recovery by ion implantation App 20060113640 - Yu; Hsiu-Mei ; et al.	2006-06-01
Method of making and structure for LDMOS transistor App 20060033155 - Wu; You-Kuo ; et al.	2006-02-16
Method of forming high voltage devices with retrograde well App 20050285218 - Wu, Kuo-Ming ; et al.	2005-12-29
High voltage semiconductor device utilizing a deep trench structure App 20050224896 - Wu, Chen-Bau ; et al.	2005-10-13
Programmable MOS device formed by stressing polycrystalline silicon App 20050185441 - Chen, Chung-Hui ; et al.	2005-08-25
Method of forming gate oxide layers with multiple thicknesses on substrate App 20050112824 - Jong, Yu-Chang ; et al.	2005-05-26
Novel method to improve bump reliability for flip chip device App 20040180296 - Chen, Yen-Ming ; et al.	2004-09-16
Method for improving bump reliability for flip chip devices Grant 6,756,294 - Chen , et al. June 29, 2	2004-06-29
Method for forming optoelectronic microelectronic fabrication with attenuated bond pad corrosion Grant 6,338,976 - Huang , et al. January 15, 2	2002-01-15
Method for alignment mark regeneration Grant 5,872,042 - Hsu , et al. February 16, 1	1999-02-16
Post tungsten etch bank anneal, to improve aluminum step coverage Grant 5,866,947 - Wang , et al. February 2, 1	1999-02-02
Method for forming high contrast alignment marks Grant 5,858,854 - Tsai , et al. January 12, 1	1999-01-12
Method of forming a tungsten silicide capacitor having a high breakdown voltage Grant 5,804,488 - Shih , et al. September 8, 1	1998-09-08
CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation Grant 5,757,045 - Tsai , et al. May 26, 1	1998-05-26
Recovery of alignment marks and laser marks after chemical-mechanical-polishing Grant 5,705,320 - Hsu , et al. January 6, 1	1998-01-06
Method of fabricating MOSFET devices Grant 5,702,972 - Tsai , et al. December 30, 1	1997-12-30
MOS device structure and integration method Grant 5,691,212 - Tsai , et al. November 25, 1	1997-11-25
CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process Grant 5,668,024 - Tsai , et al. September 16, 1	1997-09-16
Chemical/mechanical planarization (CMP) endpoint method using measurement of polishing pad temperature Grant 5,597,442 - Chen , et al. January 28, 1	1997-01-28
Method of making high precision w-polycide-to-poly capacitors in digital/analog process Grant 5,554,558 - Hsu , et al. September 10, 1	1996-09-10
Method for shielding polysilicon resistors from hydrogen intrusion Grant 5,530,418 - Hsu , et al. June 25, 1	1996-06-25
Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process Grant 5,480,828 - Hsu , et al. January 2, 1	1996-01-02
Method of making a real time ion implantation metal silicide monitor Grant 5,451,529 - Hsu , et al. September 19, 1	1995-09-19
Method for fabrication of w-polycide-to-poly capacitors with high linearity Grant 5,338,701 - Hsu , et al. August 16, 1	1994-08-16
Method of making a recessed gate MOSFET device structure Grant 5,108,937 - Tsai , et al. April 28, 1	1992-04-28

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