Hsu; Jen-Shou

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hsu; Jen-Shou.The latest application filed is for "synchronization circuit and cascaded synchronization circuit for converting asynchronous signal into synchronous signal".

Company Profile

1.21.16

Hsu; Jen-Shou - Hsinchu TW
Hsu; Jen-Shou - Hsinchu City TW
Hsu; Jen Shou - Hsin-Chu TW
Hsu; Jen-Shou - Tainan TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Data first-in first-out (FIFO) circuit Grant 11,100,963 - Wu , et al. August 24, 2	2021-08-24
Synchronization circuit and cascaded synchronization circuit for converting asynchronous signal into synchronous signal Grant 11,073,862 - Hsu July 27, 2	2021-07-27
Synchronization Circuit And Cascaded Synchronization Circuit For Converting Asynchronous Signal Into Synchronous Signal App 20210072785 - Hsu; Jen-Shou	2021-03-11
Target row refresh mechanism capable of effectively determining target row address to effectively mitigate row hammer errors without using counter circuit Grant 10,916,293 - Lai , et al. February 9, 2	2021-02-09
Test system and device Grant 9,575,114 - Hsu , et al. February 21, 2	2017-02-21
Semiconductor memory device having compression test mode Grant 9,484,117 - Hsu November 1, 2	2016-11-01
Test System And Device App 20150019927 - HSU; Jen-Shou ; et al.	2015-01-15
Semiconductor Memory Device Having Compression Test Mode App 20140301149 - HSU; Jen-Shou	2014-10-09
Repairing circuit for memory circuit and method thereof and memory circuit using the same Grant 8,472,265 - Hsu June 25, 2	2013-06-25
Delay line circuit and phase interpolation module thereof Grant 8,384,459 - Hsu February 26, 2	2013-02-26
Repairing Circuit For Memory Circuit And Method Thereof And Memory Circuit Using The Same App 20120287737 - Hsu; Jen-Shou	2012-11-15
Delay Line Circuit And Phase Interpolation Module Thereof App 20120286838 - Hsu; Jen-Shou	2012-11-15
Semiconductor memory device and method of testing the same Grant 8,289,795 - Hsu October 16, 2	2012-10-16
Memory testing system and memory module thereof Grant 7,817,485 - Hsu , et al. October 19, 2	2010-10-19
Trigger circuit of a column redundant circuit and related column redundant device Grant 7,796,448 - Hsu September 14, 2	2010-09-14
Charge pump circuit for high voltage generation Grant 7,741,898 - Hsu June 22, 2	2010-06-22
Method for detecting erroneous word lines of a memory array and device thereof Grant 7,623,388 - Chen , et al. November 24, 2	2009-11-24
Memory testing system and memory module thereof App 20090273996 - Hsu; Jen-Shou ; et al.	2009-11-05
Trigger Circuit of a Column Redundant Circuit and Related Column Redundant Device App 20090268530 - Hsu; Jen-Shou	2009-10-29
Charge pump circuit control system Grant 7,570,104 - Hsu August 4, 2	2009-08-04
Method for detecting erroneous word lines of a memory array and device thereof App 20090175097 - Chen; Tzu-Hao ; et al.	2009-07-09
Decoupling capacitor circuit Grant 7,551,018 - Hsu , et al. June 23, 2	2009-06-23
Negative voltage generator Grant 7,479,775 - Hsu January 20, 2	2009-01-20
Calibrated built-in temperature sensor and calibration method thereof Grant 7,434,985 - Hsu , et al. October 14, 2	2008-10-14
Charge pump circuit for high voltage generation App 20080174360 - Hsu; Jen-Shou	2008-07-24
Decoupling capacitor circuit App 20080142924 - Hsu; Jen Shou ; et al.	2008-06-19
Charge pump circuit control system App 20080074170 - Hsu; Jen Shou	2008-03-27
Negative voltage generator App 20080018318 - Hsu; Jen Shou	2008-01-24
Internal power management scheme for a memory chip in deep power down mode Grant 7,292,494 - Hsu , et al. November 6, 2	2007-11-06
Multiple power supplies for the driving circuit of local word line driver of DRAM Grant 7,277,315 - Yuan , et al. October 2, 2	2007-10-02
Calibrated built-in temperature sensor and calibration method thereof App 20070140308 - Hsu; Jen-Shou ; et al.	2007-06-21
Multiple power supplies for the driving circuit of local word line driver of DRAM App 20070133317 - Yuan; Der-Min ; et al.	2007-06-14
Internal power management scheme for a memory chip in deep power down mode App 20060146636 - Hsu; Jen-Shou ; et al.	2006-07-06
Speeding up the power-up procedure for low power RAM Grant 7,002,870 - Hsu February 21, 2	2006-02-21
Speeding Up The Power-up Procedure For Low Power Ram App 20050270881 - Hsu, Jen-Shou	2005-12-08

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.