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Electronic device capable of installing different modules and case module thereof
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Electronic Device Capable Of Installing Different Modules And Case Module Thereof
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Server Apparatus And Fixing Mechanism Thereof
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Method And Apparatus For Throttling Uplink Data Based On Temperature State
App 20160183117 - HSU; Fu-Chieh ; et al. | 2016-06-23 |
Class-d Amplifier
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Event-based Bio-signal Capturing System
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Systematic method for variable layout shrink
Grant 8,286,119 - Hsu , et al. October 9, 2 | 2012-10-09 |
Electrical fuse circuit for security applications
Grant 8,030,181 - Chung , et al. October 4, 2 | 2011-10-04 |
Electrical Fuse Circuit For Security Applications
App 20100329061 - Chung; Shine ; et al. | 2010-12-30 |
Electrical fuse circuit for security applications
Grant 7,821,041 - Chung , et al. October 26, 2 | 2010-10-26 |
Systematic Method for Variable Layout Shrink
App 20100199238 - Hsu; Fu-Chieh ; et al. | 2010-08-05 |
Error detection/correction method
Grant 7,634,707 - Leung , et al. December 15, 2 | 2009-12-15 |
Circuit and method for an SRAM with two phase word line pulse
Grant 7,505,345 - Wang , et al. March 17, 2 | 2009-03-17 |
Electrical Fuse Circuit for Security Applications
App 20080283963 - Chung; Shine ; et al. | 2008-11-20 |
Error Detection/Correction Method
App 20080209303 - Leung; Wingyu ; et al. | 2008-08-28 |
Circuit and method for an SRAM with two phase word line pulse
App 20080106963 - Wang; Chia Wei ; et al. | 2008-05-08 |
Fabrication Process For Increased Capacitance In An Embedded DRAM Memory
App 20080093645 - Sinitsky; Dennis ; et al. | 2008-04-24 |
Transparent error correcting memory
Grant 7,353,438 - Leung , et al. April 1, 2 | 2008-04-01 |
Fabrication process for increased capacitance in an embedded DRAM memory
Grant 7,323,379 - Sinitsky , et al. January 29, 2 | 2008-01-29 |
High speed memory system
Grant 7,206,913 - Hsu , et al. April 17, 2 | 2007-04-17 |
Fabrication process for increased capacitance in an embedded DRAM memory
App 20060172504 - Sinitsky; Dennis ; et al. | 2006-08-03 |
Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
Grant 7,056,785 - Hsu June 6, 2 | 2006-06-06 |
Error correcting memory and method of operating same
Grant 7,051,264 - Leung , et al. May 23, 2 | 2006-05-23 |
Method of fabricating vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
Grant 6,964,895 - Hsu November 15, 2 | 2005-11-15 |
Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
Grant 6,913,964 - Hsu July 5, 2 | 2005-07-05 |
Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
App 20050074935 - Hsu, Fu-Chieh | 2005-04-07 |
Transparent error correcting memory
App 20050044467 - Leung, Wingyu ; et al. | 2005-02-24 |
High speed memory system
App 20050027929 - Hsu, Fu-Chieh ; et al. | 2005-02-03 |
Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
Grant 6,841,821 - Hsu January 11, 2 | 2005-01-11 |
Latched sense amplifiers as high speed memory in a memory system
App 20040260983 - Leung, Wing Yu ; et al. | 2004-12-23 |
Non-volatile memory with crown electrode to increase capacitance between control gate and floating gate
Grant 6,808,169 - Hsu , et al. October 26, 2 | 2004-10-26 |
Method of fabricating a DRAM cell having a thin dielectric access transistor and a thick dielectric storage
Grant 6,784,048 - Leung , et al. August 31, 2 | 2004-08-31 |
Memory array with read/write methods
Grant 6,754,746 - Leung , et al. June 22, 2 | 2004-06-22 |
Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
App 20040104407 - Hsu, Fu-Chieh | 2004-06-03 |
DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
Grant 6,744,676 - Leung , et al. June 1, 2 | 2004-06-01 |
Latched sense amplifiers as high speed memory in a memory system
Grant 6,717,864 - Leung , et al. April 6, 2 | 2004-04-06 |
One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
App 20040061148 - Hsu, Fu-Chieh | 2004-04-01 |
Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
Grant 6,686,624 - Hsu February 3, 2 | 2004-02-03 |
One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
Grant 6,661,042 - Hsu December 9, 2 | 2003-12-09 |
Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
Grant 6,654,295 - Leung , et al. November 25, 2 | 2003-11-25 |
DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
Grant 6,642,098 - Leung , et al. November 4, 2 | 2003-11-04 |
One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
App 20030168677 - Hsu, Fu-Chieh | 2003-09-11 |
Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
App 20030168680 - Hsu, Fu-Chieh | 2003-09-11 |
DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
App 20030151072 - Leung, Wingyu ; et al. | 2003-08-14 |
DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
App 20030151071 - Leung, Wingyu ; et al. | 2003-08-14 |
Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
App 20030147277 - Hsu, Fu-Chieh | 2003-08-07 |
High speed memory system
App 20030097535 - Hsu, Fu-Chieh ; et al. | 2003-05-22 |
Error correcting memory and method of operating same
App 20030093744 - Leung, Wingyu ; et al. | 2003-05-15 |
Latched sense amplifiers as high speed memory in a memory system
App 20030051091 - Leung, Wing Yu ; et al. | 2003-03-13 |
Non-volatile memory embedded in a conventional logic process
Grant 6,512,691 - Hsu , et al. January 28, 2 | 2003-01-28 |
Apparatus for controlling data transfer between a bus and memory array and method for operating same
Grant 6,510,492 - Hsu , et al. January 21, 2 | 2003-01-21 |
Method of fabricating a DRAM cell having a thin dielectric access transistor and a thick dielectric storage capacitor
App 20030001181 - Leung, Wingyu ; et al. | 2003-01-02 |
Memory modules with high speed latched sense amplifiers
Grant 6,483,755 - Leung , et al. November 19, 2 | 2002-11-19 |
Non-volatile memory embedded in a conventional logic process
App 20020154541 - Hsu, Fu-Chieh ; et al. | 2002-10-24 |
Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory
Grant 6,457,108 - Hsu , et al. September 24, 2 | 2002-09-24 |
High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process
Grant 6,442,060 - Leung , et al. August 27, 2 | 2002-08-27 |
DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
App 20020094697 - Leung, Wingyu ; et al. | 2002-07-18 |
Dynamic address mapping and redundancy in a modular memory device
Grant 6,393,504 - Leung , et al. May 21, 2 | 2002-05-21 |
Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
App 20020053691 - Leung, Wingyu ; et al. | 2002-05-09 |
Method and structure of ternary CAM cell in logic process
Grant 6,370,052 - Hsu , et al. April 9, 2 | 2002-04-09 |
Non-volatile memory system
App 20020008271 - Hsu, Fu-Chieh ; et al. | 2002-01-24 |
Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
App 20010052610 - Leung, Wingyu ; et al. | 2001-12-20 |
Non-volatile memory cell and methods of fabricating and operating same
Grant 6,329,240 - Hsu , et al. December 11, 2 | 2001-12-11 |
Memory with large number of memory modules
App 20010039601 - Leung, Wing Yu ; et al. | 2001-11-08 |
Apparatus for controlling data transfer between a bus and memory array and method for operating same
App 20010037428 - Hsu, Fu-Chieh ; et al. | 2001-11-01 |
Method of operating memory array with write buffers and related apparatus
Grant 6,295,593 - Hsu , et al. September 25, 2 | 2001-09-25 |
Data processing system with master and slave devices and asymmetric signal swing bus
Grant 6,272,577 - Leung , et al. August 7, 2 | 2001-08-07 |
On-chip word line voltage generation for DRAM embedded in logic process
Grant 6,147,914 - Leung , et al. November 14, 2 | 2000-11-14 |
Memory cell for DRAM embedded in logic
Grant 6,075,720 - Leung , et al. June 13, 2 | 2000-06-13 |
Multi-port DRAM cell and memory system using same
Grant 5,923,593 - Hsu , et al. July 13, 1 | 1999-07-13 |
Circuit module redundancy architecture process
Grant 5,843,799 - Hsu , et al. December 1, 1 | 1998-12-01 |
Termination circuit with power-down mode for use in circuit module architecture
Grant 5,831,467 - Leung , et al. November 3, 1 | 1998-11-03 |
Method and structure for implementing a cache memory using a DRAM array
Grant 5,829,026 - Leung , et al. October 27, 1 | 1998-10-27 |
Method and structure for improving display data bandwidth in a unified memory architecture system
Grant 5,790,138 - Hsu August 4, 1 | 1998-08-04 |
Termination circuits for reduced swing signal lines and methods for operating same
Grant 5,729,152 - Leung , et al. March 17, 1 | 1998-03-17 |
Fault-tolerant hierarchical bus system and method of operating same
Grant 5,666,480 - Leung , et al. September 9, 1 | 1997-09-09 |
Resynchronization circuit for a memory system and method of operating same
Grant 5,655,113 - Leung , et al. August 5, 1 | 1997-08-05 |
Method and circuit for communication between a module and a bus controller in a wafer-scale integrated circuit system
Grant 5,613,077 - Leung , et al. March 18, 1 | 1997-03-18 |
Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system
Grant 5,592,632 - Leung , et al. January 7, 1 | 1997-01-07 |
Wafer-scale integrated circuit interconnect structure architecture
Grant 5,576,554 - Hsu November 19, 1 | 1996-11-19 |
Pseudo-nonvolatile memory incorporating data refresh operation
Grant 5,511,020 - Hu , et al. April 23, 1 | 1996-04-23 |
Circuit module redundancy architecture
Grant 5,498,886 - Hsu , et al. March 12, 1 | 1996-03-12 |
Programmable antifuse structure, process, logic cell and architecture for programmable integrated circuits
Grant 5,166,556 - Hsu , et al. November 24, 1 | 1992-11-24 |
Static random access memory cell using a P/N-MOS transistors
Grant 5,128,731 - Lien , et al. July 7, 1 | 1992-07-07 |
Contact sensing for integrated circuit testing
Grant 5,019,771 - Yang , et al. May 28, 1 | 1991-05-28 |
Static ram cell with trench pull-down transistors and buried-layer ground plate
Grant 4,997,783 - Hsu * March 5, 1 | 1991-03-05 |
Process for forming lightly-doped-drain (LDD) without extra masking steps
Grant 4,843,023 - Chiu , et al. June 27, 1 | 1989-06-27 |
Static ram cell with trench pull-down transistors and buried-layer ground plate
Grant 4,794,561 - Hsu December 27, 1 | 1988-12-27 |
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