Hsu; Chi-Chan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hsu; Chi-Chan.The latest application filed is for "multiple-capture dft system for scan-based integrated circuits".

Company Profile

0.4.7

Hsu; Chi-Chan - Hsinchu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multiple-capture DFT system for scan-based integrated circuits Grant 7,904,773 - Wang , et al. March 8, 2	2011-03-08
Multiple-Capture DFT system for scan-based integrated circuits App 20090070646 - Wang; Laung-Terng (L.T.) ; et al.	2009-03-12
Method and apparatus for unifying self-test with scan-test during prototype debug and production test App 20090037786 - Wang; Laung-Terng ; et al.	2009-02-05
Method and apparatus for unifying self-test with scan-test during prototype debug and production test Grant 7,444,567 - Wang , et al. October 28, 2	2008-10-28
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques Grant 7,191,373 - Wang , et al. March 13, 2	2007-03-13
Multiple-capture DFT system for scan-based integrated circuits App 20050235186 - Wang, Laung-Terng ; et al.	2005-10-20
Multiple-capture DFT system for scan-based integrated circuits Grant 6,954,887 - Wang , et al. October 11, 2	2005-10-11
Method and apparatus for unifying self-test with scan-test during prototype debug and production test App 20040268181 - Wang, Laung-Terng ; et al.	2004-12-30
Method and system to optimize test cost and disable defects for scan and BIST memories App 20020194558 - Wang, Laung-Terng ; et al.	2002-12-19
Multiple-capture DFT system for scan-based integrated circuits App 20020184560 - Wang, Laung-Terng ; et al.	2002-12-05
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques App 20020138801 - Wang, Laung-Terng ; et al.	2002-09-26

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