Hsieh; Te-Hsien
Patent Applications and Registrations
Patent applications and USPTO patent grants for Hsieh; Te-Hsien.The latest application filed is for "via landing on first and second barrier layers to reduce cleaning time of conductive structure".
- Hsieh; Te-Hsien - Hsinchu TW
- Hsieh; Te-Hsien - Kaohsiung City TW
- Hsieh; Te-Hsien - Hsin-Chu TW
- Hsieh; Te-Hsien - Kaohsiung TW
- Hsieh; Te-Hsien - Kaoshiung N/A TW
- Hsieh; Te-Hsien - Kaohsiung County TW
| Patent | Date |
|---|---|
| Via Landing On First And Second Barrier Layers To Reduce Cleaning Time Of Conductive Structure App 20220293515 - Hsieh; Te-Hsien ; et al. | 2022-09-15 |
| Ion Beam Etching Chamber With Etching By-product Redistributor App 20220148856 - Hsieh; Te-Hsien ; et al. | 2022-05-12 |
| Ion beam etching chamber with etching by-product redistributor Grant 11,239,060 - Hsieh , et al. February 1, 2 | 2022-02-01 |
| High Density Memory Devices With Low Cell Leakage And Methods For Forming The Same App 20210375993 - Hsieh; Te-Hsien ; et al. | 2021-12-02 |
| 3d Rram Cell Structure For Reducing Forming And Set Voltages App 20210366987 - Hsieh; Te-Hsien ; et al. | 2021-11-25 |
| 3D RRAM cell structure for reducing forming and set voltages Grant 11,088,203 - Hsieh , et al. August 10, 2 | 2021-08-10 |
| 3d Rram Cell Structure For Reducing Forming And Set Voltages App 20210036057 - Hsieh; Te-Hsien ; et al. | 2021-02-04 |
| Ion Beam Etching Chamber App 20190371574 - Hsieh; Te-Hsien ; et al. | 2019-12-05 |
| Pattern verifying method Grant 9,785,046 - Hsieh , et al. October 10, 2 | 2017-10-10 |
| Method for optimizing an integrated circuit layout design Grant 9,747,404 - Kuo , et al. August 29, 2 | 2017-08-29 |
| Method For Optimizing An Integrated Circuit Layout Design App 20170024506 - Kuo; Shih-Ming ; et al. | 2017-01-26 |
| Pattern Verifying Method App 20160147140 - Hsieh; Te-Hsien ; et al. | 2016-05-26 |
| Method and apparatus for integrated circuit design Grant 9,262,820 - Hsieh , et al. February 16, 2 | 2016-02-16 |
| Method And Apparatus For Integrated Circuit Design App 20150332449 - HSIEH; Te-Hsien ; et al. | 2015-11-19 |
| Method of optical proximity correction Grant 9,047,658 - Hsieh , et al. June 2, 2 | 2015-06-02 |
| Method Of Optical Proximity Correction App 20150125063 - Hsieh; Te-Hsien ; et al. | 2015-05-07 |
| Aperture For Photolithography App 20150036116 - Hsieh; Te-Hsien ; et al. | 2015-02-05 |
| Mask pattern and correcting method thereof Grant 8,885,917 - Hsieh , et al. November 11, 2 | 2014-11-11 |
| Method of optical proximity correction according to complexity of mask pattern Grant 8,806,391 - Hsieh , et al. August 12, 2 | 2014-08-12 |
| Method for making photomask layout Grant 8,745,547 - Kuo , et al. June 3, 2 | 2014-06-03 |
| Method Of Optical Proximity Correction According To Complexity Of Mask Pattern App 20140040837 - Hsieh; Te-Hsien ; et al. | 2014-02-06 |
| Mask Pattern And Correcting Method Thereof App 20130163850 - Hsieh; Te-Hsien ; et al. | 2013-06-27 |
| Double patterning mask set and method of forming thereof Grant 8,383,299 - Hsieh , et al. February 26, 2 | 2013-02-26 |
| Double Patterning Mask Set And Method Of Forming Thereof App 20120295186 - Hsieh; Te-Hsien ; et al. | 2012-11-22 |
| Optical proximity correction process Grant 8,283,093 - Hsieh , et al. October 9, 2 | 2012-10-09 |
| Optical Proximity Correction Process App 20110305977 - Hsieh; Te-Hsien ; et al. | 2011-12-15 |
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