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name:-0.022650957107544
name:-0.016493082046509
name:-0.0050480365753174
HSIEH; Bor Chiuan Patent Filings

HSIEH; Bor Chiuan

Patent Applications and Registrations

Patent applications and USPTO patent grants for HSIEH; Bor Chiuan.The latest application filed is for "gap patterning for metal-to-source/drain plugs in a semiconductor device".

Company Profile
6.17.20
  • HSIEH; Bor Chiuan - Taoyuan City TW
  • Hsieh; Bor Chiuan - Taoyuan TW
  • Hsieh; Bor-Chiuan - Taoyuan County TW
  • Hsieh; Bor Chiuan - TW TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Gap Patterning For Metal-to-source/drain Plugs In A Semiconductor Device
App 20220270931 - HUANG; Yu-Lien ;   et al.
2022-08-25
Hybrid Film Scheme For Self-aligned Contact
App 20220246473 - Lu; Jian-Hong ;   et al.
2022-08-04
Gap patterning for metal-to-source/drain plugs in a semiconductor device
Grant 11,355,399 - Huang , et al. June 7, 2
2022-06-07
Seamless Gap Fill
App 20220157934 - Huang; Yen-Chun ;   et al.
2022-05-19
Seamless gap fill
Grant 11,239,310 - Huang , et al. February 1, 2
2022-02-01
Gap Patterning For Metal-to-source/drain Plugs In A Semiconductor Device
App 20210366780 - HUANG; Yu-Lien ;   et al.
2021-11-25
System and method for supplying a precursor for an atomic layer deposition (ALD) process
Grant 11,053,584 - Hsieh , et al. July 6, 2
2021-07-06
Seamless Gap Fill
App 20200295131 - HUANG; Yen-Chun ;   et al.
2020-09-17
Seamless gap fill
Grant 10,672,866 - Huang , et al.
2020-06-02
System and Method for Supplying a Precursor for an Atomic Layer Deposition (ALD) Process
App 20200040450 - Hsieh; Bor-Chiuan ;   et al.
2020-02-06
FinFETs and methods of forming the same
Grant 10,510,867 - Hsieh , et al. Dec
2019-12-17
System and method for supplying a precursor for an atomic layer deposition (ALD) process
Grant 10,443,127 - Hsieh , et al. Oc
2019-10-15
FinFETs and Methods of Forming the Same
App 20190140076 - Hsieh; Bor Chiuan ;   et al.
2019-05-09
FinFETs and methods of forming the same
Grant 10,157,997 - Hsieh , et al. Dec
2018-12-18
Seamless Gap Fill
App 20180350906 - Huang; Yen-Chun ;   et al.
2018-12-06
FinFETs and Methods of Forming the Same
App 20180315830 - Hsieh; Bor Chiuan ;   et al.
2018-11-01
Seamless gap fill
Grant 10,084,040 - Huang , et al. September 25, 2
2018-09-25
Seamless Gap Fill
App 20170194424 - Huang; Yen-Chun ;   et al.
2017-07-06
High performance self aligned contacts and method of forming same
Grant 9,437,712 - Huang , et al. September 6, 2
2016-09-06
Sidewall free CESL for enlarging ILD gap-fill window
Grant 9,218,974 - Chung , et al. December 22, 2
2015-12-22
High Performance Self Aligned Contacts and Method of Forming Same
App 20150255275 - Huang; Yen-Chun ;   et al.
2015-09-10
System And Method For Supplying A Precursor For An Atomic Layer Deposition (ald) Process
App 20150125591 - HSIEH; BOR-CHIUAN ;   et al.
2015-05-07
Sidewall-free CESL for enlarging ILD gap-fill window
Grant 8,999,834 - Chung , et al. April 7, 2
2015-04-07
Method of dual epi process for semiconductor device
Grant 8,900,957 - Chung , et al. December 2, 2
2014-12-02
Method of dual EPI process for semiconductor device
Grant 8,900,956 - Chung , et al. December 2, 2
2014-12-02
Sidewall-free Cesl For Enlarging Ild Gap-fill Window
App 20140170846 - Chung; Han-Pin ;   et al.
2014-06-19
Method Of Dual Epi Process For Semicondcutor Device
App 20140073097 - Chung; Han-Pin ;   et al.
2014-03-13
Method Of Dual Epi Process For Semiconductor Device
App 20140073096 - Chung; Han-Pin ;   et al.
2014-03-13
Method of dual EPI process for semiconductor device
Grant 8,609,497 - Chung , et al. December 17, 2
2013-12-17
Sidewall-Free CESL for Enlarging ILD Gap-Fill Window
App 20130270651 - Chung; Han-Pin ;   et al.
2013-10-17
CMOS structure with multiple spacers
Grant 8,299,508 - Hsieh , et al. October 30, 2
2012-10-30
Method of Dual EPI Process For Semiconductor Device
App 20110201164 - Chung; Han-Pin ;   et al.
2011-08-18
Method of forming a shallow trench isolation structure
Grant 7,947,551 - Syue , et al. May 24, 2
2011-05-24
Isolation Structure For Semiconductor Device
App 20110084355 - Lin; Hsien-Hsin ;   et al.
2011-04-14
Cmos Structure With Multiple Spacers
App 20110031538 - HSIEH; Bor Chiuan ;   et al.
2011-02-10
Sidewall-Free CESL for Enlarging ILD Gap-Fill Window
App 20100314690 - Chung; Han-Pin ;   et al.
2010-12-16

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