loadpatents
name:-0.028532028198242
name:-0.021281957626343
name:-0.0012800693511963
Hsiao; Chia-Shun Patent Filings

Hsiao; Chia-Shun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hsiao; Chia-Shun.The latest application filed is for "reduced area dynamic random access memory (dram) cell and method for fabricating the same".

Company Profile
0.17.27
  • Hsiao; Chia-Shun - Cupertino CA
  • Hsiao; Chia Shun - Hsinchu TW
  • Hsiao; Chia-Shun - Hsin-Chu TW
  • Hsiao; Chia-Shun - Hsinchu County TW
  • Hsiao; Chia-Shun - Chung-Hua TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method of forming ONO-type sidewall with reduced bird's beak
Grant 7,910,429 - Dong , et al. March 22, 2
2011-03-22
Method for preparing a memory structure
Grant 7,582,524 - Chien , et al. September 1, 2
2009-09-01
Reduced Area Dynamic Random Access Memory (dram) Cell And Method For Fabricating The Same
App 20080268646 - Butler; Douglas Blaine ;   et al.
2008-10-30
Method of providing contact via to a surface
Grant 7,375,027 - Tsai , et al. May 20, 2
2008-05-20
Method for preparing a memory structure
App 20080050878 - Chien; Jung Wu ;   et al.
2008-02-28
Memory structure and method for preparing the same
App 20080044970 - Chien; Jung Wu ;   et al.
2008-02-21
Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing precursor and products thereof and apparatus therefor
Grant 7,323,729 - Dong , et al. January 29, 2
2008-01-29
Use of pedestals to fabricate contact openings
Grant 7,300,745 - Hsiao , et al. November 27, 2
2007-11-27
Method for simultaneously fabricating ONO-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using ISSG
Grant 7,297,597 - Dong , et al. November 20, 2
2007-11-20
Methods For Forming Floating Gate Memory Structures
App 20070264779 - Hsiao; Chia-Shun ;   et al.
2007-11-15
Floating Gate Memory Structures
App 20070187748 - Hsiao; Chia-Shun ;   et al.
2007-08-16
Semiconductor device comprising an undoped oxide barrier
App 20070090409 - Hsiao; Chia-Shun ;   et al.
2007-04-26
Method for preventing doped boron in a dielectric layer from diffusing into a substrate
App 20070093014 - Hsiao; Chia-Shun ;   et al.
2007-04-26
Reduced area dynamic random access memory (DRAM) cell and method for fabricating the same
App 20070085152 - Butler; Douglas Blaine ;   et al.
2007-04-19
Method Of Fabricating Shallow Trench Isolation Structure
App 20070072387 - Lai; Su-Chen ;   et al.
2007-03-29
Corner protection to reduce wrap around
Grant 7,196,381 - Hsiao , et al. March 27, 2
2007-03-27
Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing precursor and products thereof and apparatus therefor
App 20060211270 - Dong; Zhong ;   et al.
2006-09-21
Use of multiple etching steps to reduce lateral etch undercut
App 20060211255 - Huang; Chunchieh ;   et al.
2006-09-21
Methods for improving quality of semiconductor oxide composition formed from halogen-containing precursor
Grant 7,071,127 - Dong , et al. July 4, 2
2006-07-04
Use of multiple etching steps to reduce lateral etch undercut
Grant 7,071,115 - Huang , et al. July 4, 2
2006-07-04
Method of providing contact via to a surface
App 20060079080 - Tsai; Kuei-Chang ;   et al.
2006-04-13
Method for simultaneously fabricating ONO-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using ISSG
App 20060017092 - Dong; Zhong ;   et al.
2006-01-26
Nonvolatile memory structures and fabrication methods
Grant 6,962,848 - Leung , et al. November 8, 2
2005-11-08
Method of forming ONO-type sidewall with reduced bird's beak
App 20050227437 - Dong, Zhong ;   et al.
2005-10-13
Floating gate memory structures and fabrication methods
App 20050196913 - Hsiao, Chia-Shun ;   et al.
2005-09-08
Use of pedestals to fabricate contact openings
App 20050170578 - Hsiao, Chia-Shun ;   et al.
2005-08-04
Use of multiple etching steps to reduce lateral etch undercut
App 20050170646 - Huang, Chunchieh ;   et al.
2005-08-04
Corner protection to reduce wrap around
App 20050133828 - Hsiao, Chia-Shun ;   et al.
2005-06-23
Corner Protection To Reduce Wrap Around
App 20050054174 - Hsiao, Chia-Shun ;   et al.
2005-03-10
Corner protection to reduce wrap around
Grant 6,864,148 - Hsiao , et al. March 8, 2
2005-03-08
Floating gate memory structures and fabrication methods
App 20050037530 - Hsiao, Chia-Shun
2005-02-17
Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing precursor and products thereof and apparatus thereof
App 20040235295 - Dong, Zhong ;   et al.
2004-11-25
Nonvolatile memory structures and fabrication methods
Grant 6,821,847 - Leung , et al. November 23, 2
2004-11-23
Nonvolatile memory structures and fabrication methods
Grant 6,815,760 - Leung , et al. November 9, 2
2004-11-09
Nonvolatile memory structures and fabrication methods
App 20040087088 - Leung, Chung Wai ;   et al.
2004-05-06
Floating gate memory structures and fabrication methods
App 20040065937 - Hsiao, Chia-Shun
2004-04-08
Nonvolatile memories with floating gate spacers, and methods of fabrication
Grant 6,570,215 - Tuan , et al. May 27, 2
2003-05-27
Nonvolatile memories with floating gate spacers, and methods of fabrication
Grant 6,562,681 - Tuan , et al. May 13, 2
2003-05-13
Nonvolatile memory structures and fabrication methods
App 20030067031 - Leung, Chung Wai ;   et al.
2003-04-10
Nonvolatile memory structures and fabrication methods
App 20030068859 - Leung, Chung Wai ;   et al.
2003-04-10
Nonvolatile memories with floating gate spacers, and methods of fabrication
App 20020190307 - Tuan, Hsing T. ;   et al.
2002-12-19
Nonvolatile Memories With Floating Gate Spacers, And Methods Of Fabrication
App 20020190305 - Tuan, Hsing T. ;   et al.
2002-12-19
Two-step strap implantation of making deep trench capacitors for DRAM cells
Grant 6,291,286 - Hsiao September 18, 2
2001-09-18
Self aligned method of fabricating a DRAM with improved capacitance
Grant 5,946,568 - Hsiao , et al. August 31, 1
1999-08-31

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