Howell; Wayne John

Patent Applications and Registrations

Patent applications and USPTO patent grants for Howell; Wayne John.The latest application filed is for "multi-chip sack and method of fabrication utilizing self-aligning electrical contact array".

Company Profile

0.27.5

Howell; Wayne John - Williston VT
Howell; Wayne John - South Burlington VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array Grant 6,921,018 - Ference , et al. July 26, 2	2005-07-26
Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array Grant 6,858,941 - Ference , et al. February 22, 2	2005-02-22
Multi-chip sack and method of fabrication utilizing self-aligning electrical contact array App 20040108364 - Ference, Thomas George ; et al.	2004-06-10
Chip-on-chip interconnections of varied characterstics Grant 6,642,080 - Ference , et al. November 4, 2	2003-11-04
Wirebond passivation pad connection using heated capillary Grant 6,605,526 - Howell , et al. August 12, 2	2003-08-12
Micro-flex technology in semiconductor packages Grant 6,444,490 - Bertin , et al. September 3, 2	2002-09-03
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections Grant 6,410,431 - Bertin , et al. June 25, 2	2002-06-25
Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array App 20020070438 - Ference, Thomas George ; et al.	2002-06-13
Micro-flex technology in semiconductor packages App 20010039074 - Bertin, Claude Louis ; et al.	2001-11-08
Micro-flex technology in semiconductor packages App 20010035529 - Bertin, Claude Louis ; et al.	2001-11-01
Micro-flex technology in semiconductor packages Grant 6,300,687 - Bertin , et al. October 9, 2	2001-10-09
Highly integrated chip-on-chip packaging Grant 6,294,406 - Bertin , et al. September 25, 2	2001-09-25
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections App 20010001292 - Bertin, Claude Louis ; et al.	2001-05-17
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections Grant 6,222,276 - Bertin , et al. April 24, 2	2001-04-24
Highly integrated chip-on-chip packaging Grant 5,977,640 - Bertin , et al. November 2, 1	1999-11-02
Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit Grant 5,946,545 - Bertin , et al. August 31, 1	1999-08-31
Methods for precise definition of integrated circuit chip edges Grant 5,925,924 - Cronin , et al. July 20, 1	1999-07-20
Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module Grant 5,923,181 - Beilstein, Jr. , et al. July 13, 1	1999-07-13
Multi-view imaging apparatus Grant 5,907,178 - Baker , et al. May 25, 1	1999-05-25
Packaged electronic module and integral sensor array Grant 5,869,896 - Baker , et al. February 9, 1	1999-02-09
Method and apparatus for redirecting certain input/output connections of integrated circuit chip configurations Grant 5,815,374 - Howell September 29, 1	1998-09-29
Integrated high-performance decoupling capacitor Grant 5,811,868 - Bertin , et al. September 22, 1	1998-09-22
Semiconductor stack structures and fabrication sparing methods utilizing programmable spare circuit Grant 5,798,282 - Bertin , et al. August 25, 1	1998-08-25
Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging Grant 5,786,628 - Beilstein, Jr. , et al. July 28, 1	1998-07-28
Method and apparatus for directing the input/output connection of integrated circuit chip cube configurations Grant 5,781,413 - Howell , et al. July 14, 1	1998-07-14
Electronic modules with integral sensor arrays Grant 5,763,943 - Baker , et al. June 9, 1	1998-06-09
Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging Grant 5,719,438 - Beilstein, Jr. , et al. February 17, 1	1998-02-17
Integrated mulitchip memory module, structure and fabrication Grant 5,702,984 - Bertin , et al. December 30, 1	1997-12-30
Methods for precise definition of integrated circuit chip edges Grant 5,691,248 - Cronin , et al. November 25, 1	1997-11-25
Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module Grant 5,686,843 - Beilstein, Jr. , et al. November 11, 1	1997-11-11
Endcap chip with conductive, monolithic L-connect for multichip stack Grant 5,648,684 - Bertin , et al. July 15, 1	1997-07-15
Semiconductor chip having chip metal layer and transfer metal layer composed of same metal, and corresponding electronic module Grant 5,644,162 - Beilstein, Jr. , et al. July 1, 1	1997-07-01

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.