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Integrated Circuit With Thicker Metal Lines On Lower Metallization Layer
App 20210390240 - CHANG; Kuang-Hung ; et al. | 2021-12-16 |
Integrated circuit with thicker metal lines on lower metallization layer
Grant 11,113,443 - Chang , et al. September 7, 2 | 2021-09-07 |
Machine-learning design enablement platform
Grant 11,017,149 - Chuang , et al. May 25, 2 | 2021-05-25 |
Semiconductor Layout With Different Row Heights
App 20200402968 - ZHUANG; Hui-Zhong ; et al. | 2020-12-24 |
Machine-Learning Design Enablement Platform
App 20200272777 - CHUANG; Yi-Lin ; et al. | 2020-08-27 |
Machine-learning design enablement platform
Grant 10,678,973 - Chuang , et al. | 2020-06-09 |
Integrated Circuits And Manufacturing Methods Thereof
App 20200126986 - KESHAVARZI; Ali ; et al. | 2020-04-23 |
Integrated circuits and manufacturing methods thereof
Grant 10,535,655 - Keshavarzi , et al. Ja | 2020-01-14 |
Machine-learning Design Enablement Platform
App 20180268096 - CHUANG; Yi-Lin ; et al. | 2018-09-20 |
Method of component partitions on system on chip and device thereof
Grant 9,811,627 - Hou , et al. November 7, 2 | 2017-11-07 |
Method Of Component Partitions On System On Chip And Device Thereof
App 20170161420 - HOU; Yung-Chin ; et al. | 2017-06-08 |
Integrated Circuits And Manufacturing Methods Thereof
App 20160372469 - Keshavarzi; Ali ; et al. | 2016-12-22 |
Integrated circuits and manufacturing methods thereof
Grant 9,312,260 - Keshavarzi , et al. April 12, 2 | 2016-04-12 |
Integrated circuit design in optical shrink technology node
Grant 8,671,367 - Wang , et al. March 11, 2 | 2014-03-11 |
Method of generating RC technology file
Grant 8,671,382 - Su , et al. March 11, 2 | 2014-03-11 |
Integrated circuit design using DFM-enhanced architecture
Grant 8,631,366 - Hou , et al. January 14, 2 | 2014-01-14 |
Method of Generating RC Technology File
App 20130227514 - Su; Ke-Ying ; et al. | 2013-08-29 |
Integrated circuit layouts with power rails under bottom metal layer
Grant 8,507,957 - Hou , et al. August 13, 2 | 2013-08-13 |
Standard cells having flexible layout architecture/boundaries
Grant 8,504,972 - Hou , et al. August 6, 2 | 2013-08-06 |
Method for non-shrinkable IP integration
Grant 8,504,965 - Liu , et al. August 6, 2 | 2013-08-06 |
Layout and process of forming contact plugs
Grant 8,431,985 - Hou , et al. April 30, 2 | 2013-04-30 |
Method of generating RC technology file
Grant 8,418,112 - Su , et al. April 9, 2 | 2013-04-09 |
Integrated Circuit Layouts with Power Rails under Bottom Metal Layer
App 20120280287 - Hou; Yung-Chin ; et al. | 2012-11-08 |
Method of Generating RC Technology File
App 20120226479 - Su; Ke-Ying ; et al. | 2012-09-06 |
System on chip development with reconfigurable multi-project wafer technology
Grant 8,261,219 - Chen , et al. September 4, 2 | 2012-09-04 |
Methods for cell boundary isolation in double patterning design
Grant 8,255,837 - Lu , et al. August 28, 2 | 2012-08-28 |
Contact implement structure for high density design
Grant 8,217,469 - Hou , et al. July 10, 2 | 2012-07-10 |
Table-based DFM for accurate post-layout analysis
Grant 8,201,111 - Hou , et al. June 12, 2 | 2012-06-12 |
Design Method for Non-Shrinkable IP Integration
App 20120084745 - Liu; Hung-Yi ; et al. | 2012-04-05 |
Layout and Process of Forming Contact Plugs
App 20120032268 - Hou; Yung-Chin ; et al. | 2012-02-09 |
Integrated Circuits And Manufacturing Methods Thereof
App 20110291200 - KESHAVARZI; Ali ; et al. | 2011-12-01 |
Table-Based DFM for Accurate Post-Layout Analysis
App 20110289466 - Hou; Yung-Chin ; et al. | 2011-11-24 |
Table-based DFM for accurate post-layout analysis
Grant 8,001,494 - Hou , et al. August 16, 2 | 2011-08-16 |
Novel Contact Implement Structure For High Density Design
App 20110140203 - Hou; Yung-Chin ; et al. | 2011-06-16 |
Structure and system of mixing poly pitch cell design under default poly pitch design rules
Grant 7,932,566 - Hou , et al. April 26, 2 | 2011-04-26 |
Power gating in integrated circuits for leakage reduction
Grant 7,913,141 - Yu , et al. March 22, 2 | 2011-03-22 |
Integrated Circuit Design using DFM-Enhanced Architecture
App 20100281446 - Hou; Yung-Chin ; et al. | 2010-11-04 |
Layout architecture for improving circuit performance
Grant 7,821,039 - Tien , et al. October 26, 2 | 2010-10-26 |
Standard Cells Having Flexible Layout Architecture/Boundaries
App 20100269081 - Hou; Yung-Chin ; et al. | 2010-10-21 |
Standard cell without OD space effect in Y-direction
Grant 7,808,051 - Hou , et al. October 5, 2 | 2010-10-05 |
Method for optimally converting a circuit design into a semiconductor device
Grant 7,797,668 - Chang , et al. September 14, 2 | 2010-09-14 |
Methods for Cell Boundary Isolation in Double Patterning Design
App 20100196803 - Lu; Lee-Chung ; et al. | 2010-08-05 |
Structure and System of Mixing Poly Pitch Cell Design under Default Poly Pitch Design Rules
App 20100164614 - Hou; Yung-Chin ; et al. | 2010-07-01 |
Novel Layout Architecture For Performance Enhancement
App 20100127333 - Hou; Yung-Chin ; et al. | 2010-05-27 |
Table-based Dfm For Accurate Post-layout Analysis
App 20100095253 - HOU; Yung-Chin ; et al. | 2010-04-15 |
Standard Cell without OD Space Effect in Y-Direction
App 20100078725 - Hou; Yung-Chin ; et al. | 2010-04-01 |
Integrated Circuit Design In Optical Shrink Technology Node
App 20090326873 - Wang; Chung-Hsing ; et al. | 2009-12-31 |
Layout Architecture for Improving Circuit Performance
App 20090315079 - Tien; Li-Chun ; et al. | 2009-12-24 |
Sanity checker for integrated circuits
Grant 7,467,365 - Chang , et al. December 16, 2 | 2008-12-16 |
ECO cell for reducing leakage power
Grant 7,458,051 - Hou , et al. November 25, 2 | 2008-11-25 |
System On Chip Development With Reconfigurable Multi-project Wafer Technology
App 20080235635 - Chen; Kun-Lung ; et al. | 2008-09-25 |
System on chip development with reconfigurable multi-project wafer technology
Grant 7,401,302 - Chen , et al. July 15, 2 | 2008-07-15 |
Power gating in integrated circuits for leakage reduction
App 20080082876 - Yu; Lee-Chung ; et al. | 2008-04-03 |
Configurable logic and memory devices
Grant 7,350,177 - Chung , et al. March 25, 2 | 2008-03-25 |
Sanity checker for integrated circuits
App 20080072191 - Chang; George H. ; et al. | 2008-03-20 |
System and method for reducing leakage current of an integrated circuit
App 20070152745 - Hou; Yung-Chin ; et al. | 2007-07-05 |
ECO cell for reducing leakage power
App 20070109832 - Hou; Yung-Chin ; et al. | 2007-05-17 |
Method for optimally converting a circuit design into a semiconductor device
App 20070006117 - Chang; Gwan Sin ; et al. | 2007-01-04 |
System on chip development with reconfigurable multi-project wafer technology
App 20050257177 - Chen, Kun-Lung ; et al. | 2005-11-17 |
Configurable logic and memory devices
App 20050248366 - Chung, Shine Chien ; et al. | 2005-11-10 |
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