Hou; Yuan-Te

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hou; Yuan-Te.The latest application filed is for "integrated circuit with thicker metal lines on lower metallization layer".

Company Profile

12.78.76

Hou; Yuan-Te - Hsinchu TW
HOU; Yuan-Te - Hsinchu City TW
Hou; Yuan-Te - Hsin-Chu TW
HOU; Yuan-Te - Hsin-Chu City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Pattern formation method using a photo mask for manufacturing a semiconductor device Grant 11,294,286 - Liu , et al. April 5, 2	2022-04-05
Integrated Circuit With Thicker Metal Lines On Lower Metallization Layer App 20210390240 - CHANG; Kuang-Hung ; et al.	2021-12-16
Cell placement site optimization Grant 11,182,527 - Lin , et al. November 23, 2	2021-11-23
Constrained cell placement Grant 11,176,303 - Lin , et al. November 16, 2	2021-11-16
Block Level Design Method For Heterogeneous Pg-structure Cells App 20210326509 - LIN; Yen-Hung ; et al.	2021-10-21
Integrated circuit with thicker metal lines on lower metallization layer Grant 11,113,443 - Chang , et al. September 7, 2	2021-09-07
Leakage Analysis On Semiconductor Device App 20210264093 - LIU; Cheng-Hua ; et al.	2021-08-26
Leakage Analysis On Semiconductor Device App 20210264092 - LIU; Cheng-Hua ; et al.	2021-08-26
Block level design method for heterogeneous PG-structure cells Grant 11,055,466 - Lin , et al. July 6, 2	2021-07-06
Method, System, And Storage Medium Of Resource Planning For Designing Semiconductor Device App 20210192117 - LIN; YEN-HUNG ; et al.	2021-06-24
Leakage analysis on semiconductor device Grant 11,030,381 - Liu , et al. June 8, 2	2021-06-08
Multiple patterning method and system for implementing the method Grant 10,990,741 - Lin , et al. April 27, 2	2021-04-27
Method, system, and storage medium of resource planning for designing semiconductor device Grant 10,956,643 - Lin , et al. March 23, 2	2021-03-23
Semiconductor apparatus including uncrowned and crowned cells and method of making Grant 10,943,046 - Ray , et al. March 9, 2	2021-03-09
Variant cell height integrated circuit design Grant 10,878,157 - Lin , et al. December 29, 2	2020-12-29
Method, System, And Storage Medium Of Resource Planning For Designing Semiconductor Device App 20200265180 - LIN; YEN-HUNG ; et al.	2020-08-20
Leakage Analysis On Semiconductor Device App 20200226229 - LIU; Cheng-Hua ; et al.	2020-07-16
Cell Placement Site Optimization App 20200226316 - LIN; Yen-Hung ; et al.	2020-07-16
Method, system, and storage medium of resource planning for designing semiconductor device Grant 10,671,788 - Lin , et al.	2020-06-02
Cell placement site optimization Grant 10,642,949 - Lin , et al.	2020-05-05
Rule checking for multiple patterning technology Grant 10,643,017 - Hsu , et al.	2020-05-05
Block Level Design Method For Heterogeneous Pg-structure Cells App 20200125783 - LIN; Yen-Hung ; et al.	2020-04-23
Constrained Cell Placement App 20200082046 - Lin; Yen-Hung ; et al.	2020-03-12
Multiple Patterning Method And System For Implementing The Method App 20200074038 - LIN; Yen-Hung ; et al.	2020-03-05
Constrained cell placement Grant 10,565,341 - Lin , et al. Feb	2020-02-18
Semiconductor Apparatus Including Uncrowned And Crowned Cells And Method Of Making App 20200050733 - RAY; Prasenjit ; et al.	2020-02-13
Pattern Formation Method Using A Photo Mask For Manufacturing A Semiconductor Device App 20200004137 - LIU; Ru-Gun ; et al.	2020-01-02
Block-level design method for heterogeneous PG-structure cells Grant 10,515,175 - Lin , et al. Dec	2019-12-24
Multiple patterning method, system for implementing the method and layout formed Grant 10,489,547 - Lin , et al. Nov	2019-11-26
Method of reconfiguring uncrowned standard cells and semiconductor apparatus including uncrowned and crowned cells Grant 10,452,805 - Ray , et al. Oc	2019-10-22
System and method for assigning color pattern Grant 10,318,698 - Lin , et al.	2019-06-11
Method, System, And Storage Medium Of Resource Planning For Designing Semiconductor Device App 20190155980 - LIN; YEN-HUNG ; et al.	2019-05-23
Variant Cell Height Integrated Circuit Design App 20190147133 - Lin; Yen-Hung ; et al.	2019-05-16
Method Of Reconfiguring Uncrowned Standard Cells And Semiconductor Apparatus Including Uncrowned And Crowned Cells App 20190108305 - RAY; Prasenjit ; et al.	2019-04-11
Multiple driver pin integrated circuit structure Grant 10,177,097 - Yu , et al. J	2019-01-08
Method of reconfiguring uncrowned standard cells and semiconductor apparatus including uncrowned and crowned cells Grant 10,169,520 - Ray , et al. J	2019-01-01
Systems and methods for using multiple libraries with different cell pre-coloring Grant 10,162,929 - Hsu , et al. Dec	2018-12-25
Cell Placement Site Optimization App 20180357351 - LIN; Yen-Hung ; et al.	2018-12-13
Constrained Cell Placement App 20180330034 - Lin; Yen-Hung ; et al.	2018-11-15
Method for triple-patterning friendly placement Grant 10,089,433 - Hsu , et al. October 2, 2	2018-10-02
Design Rule Checking For Multiple Patterning Technology App 20180239862 - HSU; Meng-Kai ; et al.	2018-08-23
Layout checking method for advanced double patterning photolithography with multiple spacing criteria Grant 10,055,531 - Wang , et al. August 21, 2	2018-08-21
Semiconductor device with reduced leakage current Grant 10,050,028 - Peng , et al. August 14, 2	2018-08-14
Block-level Design Method For Heterogeneous Pg-structure Cells App 20180210993 - LIN; Yen-Hung ; et al.	2018-07-26
Multiple Driver Pin Integrated Circuit Structure App 20180204806 - YU; Chih-Yeh ; et al.	2018-07-19
System And Method For Assigning Color Pattern App 20180165406 - LIN; Yen-Hung ; et al.	2018-06-14
Semiconductor Device with Reduced Leakage Current App 20180151550 - Peng; Shih-Wei ; et al.	2018-05-31
Rule checking for multiple patterning technology Grant 9,971,863 - Hsu , et al. May 15, 2	2018-05-15
Multiple driver pin integrated circuit structure Grant 9,935,057 - Yu , et al. April 3, 2	2018-04-03
Multiple Patterning Method, System For Implementing The Method And Layout Formed App 20180068046 - LIN; Yen-Hung ; et al.	2018-03-08
Multiple Driver Pin Integrated Circuit Structure App 20180040567 - YU; Chih-Yeh ; et al.	2018-02-08
Method Of Reconfiguring Uncrowned Standard Cells And Semiconductor Apparatus Including Uncrowned And Crowned Cells App 20180004886 - RAY; Prasenjit ; et al.	2018-01-04
Method For Triple-patterning Friendly Placement App 20170323047 - HSU; Meng-Kai ; et al.	2017-11-09
Systems And Methods For Using Multiple Libraries With Different Cell Pre-coloring App 20170323046 - HSU; Meng-Kai ; et al.	2017-11-09
Integrated circuit having a staggered fishbone power network Grant 9,799,602 - Chang , et al. October 24, 2	2017-10-24
Apparatus and method for mitigating dynamic IR voltage drop and electromigration affects Grant 9,768,119 - Yu , et al. September 19, 2	2017-09-19
Design Rule Checking For Multiple Patterning Technology App 20170255740 - HSU; Meng-Kai ; et al.	2017-09-07
Layout optimization for integrated circuit design Grant 9,754,073 - Chen , et al. September 5, 2	2017-09-05
Methods for double-patterning-compliant standard cell design Grant 9,747,402 - Chen , et al. August 29, 2	2017-08-29
Integrated Circuit Having A Staggered Fishbone Power Network App 20170194252 - CHANG; Kuang-Hung ; et al.	2017-07-06
Method, system and computer program product for generating layout for semiconductor device Grant 9,659,133 - Lin , et al. May 23, 2	2017-05-23
Apparatus And Method For Mitigating Dynamic Ir Voltage Drop And Electromigration Affects App 20170133321 - YU; Chih-Yeh ; et al.	2017-05-11
Semiconductor device with self-aligned interconnects Grant 9,627,310 - Chang , et al. April 18, 2	2017-04-18
Electromigration resistant standard cell device Grant 9,558,312 - Lu , et al. January 31, 2	2017-01-31
Interconnect structure having smaller transition layer via Grant 9,553,043 - Lu , et al. January 24, 2	2017-01-24
Non-hierarchical metal layers for integrated circuits Grant 9,543,193 - Lu , et al. January 10, 2	2017-01-10
Layout Optimization for Integrated Circuit Design App 20160350473 - Chen; Huang-Yu ; et al.	2016-12-01
Tier based layer promotion and demotion Grant 9,436,793 - Lin , et al. September 6, 2	2016-09-06
Layout Checking Method For Advanced Double Patterning Photolithography With Multiple Spacing Criteria App 20160239599 - WANG; CHUNG-HSING ; et al.	2016-08-18
Layout optimization for integrated circuit design Grant 9,418,196 - Chen , et al. August 16, 2	2016-08-16
Semiconductor arrangement formation Grant 9,405,880 - Lin , et al. August 2, 2	2016-08-02
Double patterning technology (DPT) layout routing Grant 9,317,650 - Chen , et al. April 19, 2	2016-04-19
Layout optimization for integrated circuit design Grant 9,292,645 - Chen , et al. March 22, 2	2016-03-22
Method and system for multi-patterning layout decomposition Grant 9,223,924 - Hsu , et al. December 29, 2	2015-12-29
Non-Hierarchical Metal Layers for Integrated Circuits App 20150364359 - Lu; Lee-Chung ; et al.	2015-12-17
Semiconductor Arrangement Formation App 20150331990 - Lin; Yen-Hung ; et al.	2015-11-19
Electromigration Resistant Standard Cell Device App 20150248517 - LU; Lee-Chung ; et al.	2015-09-03
Non-hierarchical metal layers for integrated circuits Grant 9,117,882 - Lu , et al. August 25, 2	2015-08-25
Tier Based Layer Promotion And Demotion App 20150213178 - Lin; Yen-Hung ; et al.	2015-07-30
Cell layout design and method Grant 9,087,170 - Hsu , et al. July 21, 2	2015-07-21
Layout Optimization For Integrated Circuit Design App 20150199469 - Chen; Huang-Yu ; et al.	2015-07-16
Generating database for cells routable in pin layer Grant 9,064,081 - Hsu , et al. June 23, 2	2015-06-23
Generating Database For Cells Routable In Pin Layer App 20150161319 - HSU; MENG-KAI ; et al.	2015-06-11
Electromigration resistant standard cell device Grant 9,035,361 - Lu , et al. May 19, 2	2015-05-19
Method, System And Computer Program Product For Generating Layout For Semiconductor Device App 20150113493 - LIN; Yen-Hung ; et al.	2015-04-23
Methods for Double-Patterning-Compliant Standard Cell Design App 20150095870 - Chen; Huang-Yu ; et al.	2015-04-02
Method And System For Multi-patterning Layout Decomposition App 20150095857 - HSU; Chin-Hsiung ; et al.	2015-04-02
Layout Optimization For Integrated Circuit Design App 20150082259 - CHEN; HUANG-YU ; et al.	2015-03-19
Method and system for replacing a pattern in a layout Grant 8,977,991 - Chen , et al. March 10, 2	2015-03-10
Cell Layout Design And Method App 20150067616 - HSU; Chin-Hsiung ; et al.	2015-03-05
Routing method Grant 8,972,910 - Hou , et al. March 3, 2	2015-03-03
Routing Method App 20150052492 - HOU; Yuan-Te ; et al.	2015-02-19
Systems and methods for designing layouts for semiconductor device fabrication Grant 8,959,466 - Hsu , et al. February 17, 2	2015-02-17
Double Patterning Technology (dpt) Layout Routing App 20150012895 - Chen; Huang-Yu ; et al.	2015-01-08
Layout re-decomposition for multiple patterning layouts Grant 8,914,755 - Hsu , et al. December 16, 2	2014-12-16
Methods for double-patterning-compliant standard cell design Grant 8,907,441 - Chen , et al. December 9, 2	2014-12-09
Semiconductor device with self-aligned interconnects and blocking portions Grant 8,907,497 - Chang , et al. December 9, 2	2014-12-09
Layout Re-decomposition For Multiple Patterning Layouts App 20140359544 - Hsu; Chin-Hsiung ; et al.	2014-12-04
Layout optimization for integrated design Grant 8,898,600 - Chen , et al. November 25, 2	2014-11-25
Reusable cut mask for multiple layers Grant 8,875,067 - Hsu , et al. October 28, 2	2014-10-28
Integrated circuit layout modification Grant 8,856,696 - Chen , et al. October 7, 2	2014-10-07
Double patterning technology (DPT) layout routing Grant 8,850,368 - Chen , et al. September 30, 2	2014-09-30
Reusable Cut Mask For Multiple Layers App 20140282287 - Hsu; Chin-Hsiung ; et al.	2014-09-18
Apparatus And Method For Mitigating Dynamic Ir Voltage Drop And Electromigration Affects App 20140264924 - YU; Chih-Yeh ; et al.	2014-09-18
Layout Optimization for Integrated Design App 20140282306 - Chen; Huang-Yu ; et al.	2014-09-18
Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed Grant 8,826,212 - Yeh , et al. September 2, 2	2014-09-02
Double Patterning Technology (dpt) Layout Routing App 20140215428 - Chen; Huang-Yu ; et al.	2014-07-31
Method Of Forming A Layout Including Cells Having Different Threshold Voltages, A System Of Implementing And A Layout Formed App 20140165020 - YEH; Sung-Yen ; et al.	2014-06-12
Method And System For Replacing A Pattern In A Layout App 20140059504 - CHEN; Huang-Yu ; et al.	2014-02-27
Integrated circuit design using DFM-enhanced architecture Grant 8,631,366 - Hou , et al. January 14, 2	2014-01-14
Method and system for replacing a pattern in a layout Grant 8,601,408 - Chen , et al. December 3, 2	2013-12-03
Cell layout for multiple patterning technology Grant 8,584,052 - Chen , et al. November 12, 2	2013-11-12
Semiconductor Device With Self-Aligned Interconnects and Blocking Portions App 20130285246 - Chang; Shih-Ming ; et al.	2013-10-31
Semiconductor Device with Self-Aligned Interconnects App 20130270704 - Chang; Shih-Ming ; et al.	2013-10-17
Interconnect Structure Having Smaller Transition Layer Via App 20130256902 - LU; Lee-Chung ; et al.	2013-10-03
Electromigration Resistant Standard Cell Device App 20130234212 - LU; Lee-Chung ; et al.	2013-09-12
Coloring/grouping Patterns For Multi-patterning App 20130205266 - Chen; Wen-Hao ; et al.	2013-08-08
Integrated Circuit Layout Modification App 20130191796 - CHEN; Wen-Hao ; et al.	2013-07-25
Tool and method for eliminating multi-patterning conflicts Grant 8,448,100 - Lin , et al. May 21, 2	2013-05-21
Electromigration resistant standard cell device Grant 8,431,968 - Lu , et al. April 30, 2	2013-04-30
Method And System For Replacing A Pattern In A Layout App 20130091476 - CHEN; Huang-Yu ; et al.	2013-04-11
Method and apparatus for achieving multiple patterning technology compliant design layout Grant 8,418,111 - Chen , et al. April 9, 2	2013-04-09
Non-Hierarchical Metal Layers for Integrated Circuits App 20120313256 - Lu; Lee-Chung ; et al.	2012-12-13
Methods for cell boundary isolation in double patterning design Grant 8,255,837 - Lu , et al. August 28, 2	2012-08-28
Routing system and method for double patterning technology Grant 8,239,806 - Chen , et al. August 7, 2	2012-08-07
Double patterning technology using single-patterning-spacer-technique Grant 8,211,807 - Chen , et al. July 3, 2	2012-07-03
Cell Layout for Multiple Patterning Technology App 20120167021 - Chen; Huang-Yu ; et al.	2012-06-28
Method And Apparatus For Achieving Multiple Patterning Technology Compliant Design Layout App 20120131528 - Chen; Huang-Yu ; et al.	2012-05-24
Double Patterning Technology Using Single-Patterning-Spacer-Technique App 20120091592 - Chen; Huang-Yu ; et al.	2012-04-19
System and method for on-chip-variation analysis Grant 8,117,575 - Lu , et al. February 14, 2	2012-02-14
Electromigration Resistant Standard Cell Device App 20120025273 - LU; Lee-Chung ; et al.	2012-02-02
Methods for Double-Patterning-Compliant Standard Cell Design App 20110193234 - Chen; Huang-Yu ; et al.	2011-08-11
Routing System And Method For Double Patterning Technology App 20110119648 - Chen; Huang-Yu ; et al.	2011-05-19
System And Method For On-chip-variation Analysis App 20110035715 - Lu; Lee-Chung ; et al.	2011-02-10
Integrated Circuit Design using DFM-Enhanced Architecture App 20100281446 - Hou; Yung-Chin ; et al.	2010-11-04
Methods for Cell Boundary Isolation in Double Patterning Design App 20100196803 - Lu; Lee-Chung ; et al.	2010-08-05

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