Hou; Chin-Shan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hou; Chin-Shan.The latest application filed is for "method and apparatus for integrated circuit layout".

Company Profile

0.11.10

Hou; Chin-Shan - Hsin-Chu TW
Hou; Chin-Shan - Hsin-Chu City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for integrated circuit layout Grant 9,995,998 - Chen , et al. June 12, 2	2018-06-12
Method And Apparatus For Integrated Circuit Layout App 20160370698 - Chen; Yi-Fan ; et al.	2016-12-22
Method and apparatus for integrated circuit layout Grant 9,377,680 - Chen , et al. June 28, 2	2016-06-28
Semiconductor devices, methods of manufacture thereof, and methods of forming resistors Grant 9,111,768 - Lu , et al. August 18, 2	2015-08-18
Semiconductor device including polysilicon resistor and metal gate resistor and methods of fabricating thereof Grant 9,070,624 - Chen , et al. June 30, 2	2015-06-30
Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Resistors App 20150001678 - Lu; Chia-Yu ; et al.	2015-01-01
Semiconductor devices, methods of manufacture thereof, and methods of forming resistors Grant 8,859,386 - Lu , et al. October 14, 2	2014-10-14
Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Resistors App 20130328131 - Lu; Chia-Yu ; et al.	2013-12-12
Semiconductor Device Including Polysilicon Resistor And Metal Gate Resistor And Methods Of Fabricating Thereof App 20130157452 - Chen; Jian-Hao ; et al.	2013-06-20
Electrical Fuse Structure and Method App 20100090751 - Cheng; Hsin-Li ; et al.	2010-04-15
Electrical fuse structure and method Grant 7,642,176 - Cheng , et al. January 5, 2	2010-01-05
Electrical Fuse Structure and Method App 20090261450 - Cheng; Hsin-Li ; et al.	2009-10-22
Placement and routing method to reduce Joule heating Grant 7,155,686 - Hou , et al. December 26, 2	2006-12-26
Mixed implantation on polysilicon fuse for CMOS technology App 20050258505 - Wu, Juing-Yi ; et al.	2005-11-24
Placement and routing method to reduce Joule heating App 20050204314 - Hou, Chin-Shan ; et al.	2005-09-15
Formation of a thin oxide protection layer at poly sidewall and area surface Grant 6,074,905 - Hu , et al. June 13, 2	2000-06-13
Plasma method for stripping ion implanted photoresist layers Grant 6,024,887 - Kuo , et al. February 15, 2	2000-02-15

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