Horne; Stephen C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Horne; Stephen C..The latest application filed is for "mechanism for protecting integrated circuits from security attacks".

Company Profile

0.28.7

Horne; Stephen C. - Austin TX
Horne; Stephen C - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Device input modes with corresponding cover configurations Grant 9,645,721 - Horne May 9, 2	2017-05-09
Mechanism for protecting integrated circuits from security attacks Grant 9,405,917 - Horne August 2, 2	2016-08-02
Mechanism For Protecting Integrated Circuits From Security Attacks App 20150347762 - Horne; Stephen C	2015-12-03
Device Input Modes With Corresponding User Interfaces App 20150026623 - Horne; Stephen C.	2015-01-22
Memory including a reduced leakage wordline driver Grant 8,837,226 - McCombs , et al. September 16, 2	2014-09-16
Memory Including A Reduced Leakage Wordline Driver App 20130111130 - McCombs; Edward M. ; et al.	2013-05-02
Minimizing transistor size in integrated circuits Grant 7,026,691 - Sander , et al. April 11, 2	2006-04-11
Method and apparatus for a 1 of N signal Grant 6,911,846 - Blomgren , et al. June 28, 2	2005-06-28
Dynamic logic scan gate method and apparatus Grant 6,745,357 - Chrudimsky , et al. June 1, 2	2004-06-01
Generation of route rules Grant 6,732,346 - Horne , et al. May 4, 2	2004-05-04
Generation of route rules App 20020178428 - Horne, Stephen C. ; et al.	2002-11-28
Method For Calculating Dynamic Logic Block Propagation Delay Targets Using Time Borrowing App 20020067187 - Vijayan, Gopal ; et al.	2002-06-06
Dynamic logic scan gate method and apparatus App 20010039635 - Chrudimsky, David W. ; et al.	2001-11-08
Method and apparatus for generating clock signals Grant 6,288,589 - Potter , et al. September 11, 2	2001-09-11
Minimizing transistor size in integrated circuits Grant 6,287,953 - Sander , et al. September 11, 2	2001-09-11
Method and apparatus for logic synchronization Grant 6,268,746 - Potter , et al. July 31, 2	2001-07-31
Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock Grant 6,233,707 - Potter , et al. May 15, 2	2001-05-15
Minimizing transistor size in integrated circuits Grant 6,146,954 - Klein , et al. November 14, 2	2000-11-14
Method and apparatus for a N-nary logic circuit using capacitance isolation Grant 6,124,735 - Blomgren , et al. September 26, 2	2000-09-26
Method and apparatus for a logic circuit with constant power consumption Grant 6,107,835 - Blomgren , et al. August 22, 2	2000-08-22
Method and apparatus for a N-nary logic circuit using 1 of N signals Grant 6,069,497 - Blomgren , et al. May 30, 2	2000-05-30
Method and apparatus for a N-nary logic circuit using 1 of 4 signals Grant 6,066,965 - Blomgren , et al. May 23, 2	2000-05-23
Forming local interconnects in integrated circuits Grant 6,051,881 - Klein , et al. April 18, 2	2000-04-18
Method for self-aligning polysilicon gates with field isolation and the resultant structure Grant 6,046,088 - Klein , et al. April 4, 2	2000-04-04
Compact, dual-transistor integrated circuit Grant 5,920,097 - Horne July 6, 1	1999-07-06
Distributed gated clock driver Grant 5,892,373 - Tupuri , et al. April 6, 1	1999-04-06
Digital clock waveform generator and method for generating a clock signal Grant 5,812,832 - Horne , et al. September 22, 1	1998-09-22
Variable strength clock signal driver and method of manufacturing the same Grant 5,751,173 - McMahon , et al. May 12, 1	1998-05-12
Circuit configuration employing a compare unit for testing variably controlled delay units Grant 5,570,294 - McMinn , et al. October 29, 1	1996-10-29
Self-adjusting variable drive strength buffer circuit and method for controlling the drive strength of a buffer circuit Grant 5,444,406 - Horne August 22, 1	1995-08-22
Configuration and method for testing a delay chain within a microprocessor clock generator Grant 5,430,394 - McMinn , et al. July 4, 1	1995-07-04
Data cache and method for handling memory errors during copy-back Grant 5,295,259 - Horne March 15, 1	1994-03-15
Interlock acquisition for critical code section execution in a shared memory common-bus individually cached multiprocessor system Grant 5,289,588 - Song , et al. February 22, 1	1994-02-22

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