Hornback; Verne

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hornback; Verne.The latest application filed is for "application of gate edge liner to maintain gate length cd in a replacement gate transistor flow".

Company Profile

0.9.5

Hornback; Verne - Camas WA US
Hornback; Verne - Troutdale OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow Grant 8,384,165 - Carter , et al. February 26, 2	2013-02-26
Self-aligned cell integration scheme Grant 7,915,122 - Carter , et al. March 29, 2	2011-03-29
Application Of Gate Edge Liner To Maintain Gate Length Cd In A Replacement Gate Transistor Flow App 20080308882 - Carter; Richard J. ; et al.	2008-12-18
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow Grant 7,405,116 - Carter , et al. July 29, 2	2008-07-29
Incorporating dopants to enhance the dielectric properties of metal silicates Grant 7,312,127 - Lo , et al. December 25, 2	2007-12-25
Fabrication of trenches with multiple depths on the same substrate Grant 7,189,628 - Mirbedini , et al. March 13, 2	2007-03-13
Self-aligned cell integration scheme App 20060281256 - Carter; Richard J. ; et al.	2006-12-14
Incorporating dopants to enhance the dielectric properties of metal silicates App 20060166496 - Lo; Wai ; et al.	2006-07-27
Incorporating dopants to enhance the dielectric properties of metal silicates Grant 7,064,062 - Lo , et al. June 20, 2	2006-06-20
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow App 20060035425 - Carter; Richard J. ; et al.	2006-02-16
Incorporating dopants to enhance the dielectric properties of metal silicates App 20050127458 - Lo, Wai ; et al.	2005-06-16
Fabrication of trenches with multiple depths on the same substrate Grant 6,864,152 - Mirbedini , et al. March 8, 2	2005-03-08
Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET Grant 6,355,532 - Seliskar , et al. March 12, 2	2002-03-12

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