Horiuchi; Hidetaka

Patent Applications and Registrations

Patent applications and USPTO patent grants for Horiuchi; Hidetaka.The latest application filed is for "method of reducing coupling between floating gates in nonvolatile memory".

Company Profile

0.5.5

Horiuchi; Hidetaka - Nagoya JP
Horiuchi; Hidetaka - Hagamachi JP
Horiuchi; Hidetaka - Tochigi JP
Horiuchi, Hidetaka - Haga-gun JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of reducing coupling between floating gates in nonvolatile memory Grant 8,288,225 - Chien , et al. October 16, 2	2012-10-16
Method Of Reducing Coupling Between Floating Gates In Nonvolatile Memory App 20110111583 - Chien; Henry ; et al.	2011-05-12
Method of reducing coupling between floating gates in nonvolatile memory Grant 7,910,434 - Chien , et al. March 22, 2	2011-03-22
Method Of Reducing Coupling Between Floating Gates In Nonvolatile Memory App 20100047979 - Chien; Henry ; et al.	2010-02-25
Methods of reducing coupling between floating gates in nonvolatile memory Grant 7,615,445 - Chien , et al. November 10, 2	2009-11-10
Nonvolatile Memory with Reduced Coupling Between Floating Gates App 20080074920 - Chien; Henry ; et al.	2008-03-27
Methods of Reducing Coupling Between Floating Gates in Nonvolatile Memory App 20080076217 - Chien; Henry ; et al.	2008-03-27
Method and apparatus for processing semiconductor substrates Grant 6,558,505 - Suzuki , et al. May 6, 2	2003-05-06
Method and apparatus for processing semiconductor substrates Grant 6,547,921 - Suzuki , et al. April 15, 2	2003-04-15
Method and apparatus for processing semiconductor substrates App 20030024642 - Suzuki, Katsunori ; et al.	2003-02-06

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