Horak; David V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Horak; David V..The latest application filed is for "gate contact with vertical isolation from source-drain".

Company Profile

3.200.200

Horak; David V. - Essex Junction VT
Horak; David V. - Albany NY
Horak; David V - Essex Junction VT US
Horak; David V - Albany NY US
Horak; David V. - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Size-filtered multimetal structures Grant 10,134,631 - Horak , et al. November 20, 2	2018-11-20
Non-lithographic line pattern formation Grant 9,997,367 - Tseng , et al. June 12, 2	2018-06-12
Gate contact with vertical isolation from source-drain Grant 9,935,168 - Horak , et al. April 3, 2	2018-04-03
Gate Contact With Vertical Isolation From Source-drain App 20170170266 - Horak; David V. ; et al.	2017-06-15
Replacement gate electrode with a self-aligned dielectric spacer Grant 9,660,030 - Ponoth , et al. May 23, 2	2017-05-23
Borderless contact structure Grant 9,620,619 - Basker , et al. April 11, 2	2017-04-11
Gate contact with vertical isolation from source-drain Grant 9,614,047 - Horak , et al. April 4, 2	2017-04-04
Replacement metal gate Grant 9,515,070 - Horak , et al. December 6, 2	2016-12-06
Non-lithographic Line Pattern Formation App 20160329214 - Tseng; Chiahsun ; et al.	2016-11-10
Size-filtered multimetal structures Grant 9,484,254 - Horak , et al. November 1, 2	2016-11-01
Gate Contact With Vertical Isolation From Source-drain App 20160260812 - Horak; David V. ; et al.	2016-09-08
Non-lithographic line pattern formation Grant 9,396,957 - Tseng , et al. July 19, 2	2016-07-19
Size-filtered Multimetal Structures App 20160204064 - Horak; David V. ; et al.	2016-07-14
Integrated circuit structure having selectively formed metal cap Grant 9,379,198 - Yang , et al. June 28, 2	2016-06-28
Dual hard mask lithography process Grant 9,373,580 - Arnold , et al. June 21, 2	2016-06-21
Silicon-on-insulator transistor with self-aligned borderless source/drain contacts Grant 9,368,590 - Fan , et al. June 14, 2	2016-06-14
Gate contact with vertical isolation from source-drain Grant 9,349,598 - Horak , et al. May 24, 2	2016-05-24
Microelectronic structure including air gap Grant 9,332,628 - Edelstein , et al. May 3, 2	2016-05-03
Non-lithographic hole pattern formation Grant 9,330,962 - Tseng , et al. May 3, 2	2016-05-03
Replacement Metal Gate App 20160086944 - Horak; David V. ; et al.	2016-03-24
Integrated circuits having gate cap protection and methods of forming the same Grant 9,269,611 - Pham , et al. February 23, 2	2016-02-23
Dual damascene dual alignment interconnect scheme Grant 9,269,621 - Holmes , et al. February 23, 2	2016-02-23
Sub-lithographic semiconductor structures with non-constant pitch Grant 9,263,290 - Bergendahl , et al. February 16, 2	2016-02-16
Overlay-tolerant via mask and reactive ion etch (RIE) technique Grant 9,263,388 - Holmes , et al. February 16, 2	2016-02-16
Replacement metal gate Grant 9,231,080 - Horak , et al. January 5, 2	2016-01-05
Sub-lithographic Semiconductor Structures With Non-constant Pitch App 20150380262 - Bergendahl; Marc A. ; et al.	2015-12-31
Gate Contact With Vertical Isolation From Source-drain App 20150357409 - Horak; David V. ; et al.	2015-12-10
Mask free protection of work function material portions in wide replacement gate electrodes Grant 9,202,879 - Koburger, III , et al. December 1, 2	2015-12-01
Recessing And Capping Of Gate Structures With Varying Metal Compositions App 20150340462 - XIE; Ruilong ; et al.	2015-11-26
Sub-lithographic semiconductor structures with non-constant pitch Grant 9,177,820 - Bergendahl , et al. November 3, 2	2015-11-03
Copper interconnect structures and methods of making same Grant 9,159,653 - Yang , et al. October 13, 2	2015-10-13
Microelectronic Structure Including Air Gap App 20150289361 - Edelstein; Daniel C. ; et al.	2015-10-08
Gate contact with vertical isolation from source-drain Grant 9,147,576 - Horak , et al. September 29, 2	2015-09-29
Replacement Metal Gate App 20150270373 - Horak; David V. ; et al.	2015-09-24
Interconnect structures and methods for back end of the line integration Grant 9,141,749 - Horak , et al. September 22, 2	2015-09-22
Recessing and capping of gate structures with varying metal compositions Grant 9,130,029 - Xie , et al. September 8, 2	2015-09-08
Profile control in interconnect structures Grant 9,105,641 - Chen , et al. August 11, 2	2015-08-11
Microelectronic structure including air gap Grant 9,105,693 - Edelstein , et al. August 11, 2	2015-08-11
Overlay-tolerant Via Mask And Reactive Ion Etch (rie) Technique App 20150221591 - Holmes; Steven J. ; et al.	2015-08-06
Gate Contact With Vertical Isolation From Source-drain App 20150206754 - Horak; David V. ; et al.	2015-07-23
Integrated Circuits Having Gate Cap Protection And Methods Of Forming The Same App 20150206844 - Pham; Daniel Thanh Khae ; et al.	2015-07-23
Bi-layer gate cap for self-aligned contact formation Grant 9,064,801 - Horak , et al. June 23, 2	2015-06-23
Microelectronic structure including air gap Grant 9,059,251 - Edelstein , et al. June 16, 2	2015-06-16
Overlay-tolerant via mask and reactive ion etch (RIE) technique Grant 9,059,254 - Holmes , et al. June 16, 2	2015-06-16
Replacement gate MOSFET with raised source and drain Grant 9,059,270 - Ponoth , et al. June 16, 2	2015-06-16
Non-lithographic hole pattern formation Grant 9,054,156 - Tseng , et al. June 9, 2	2015-06-09
Borderless Contact For Ultra-thin Body Devices App 20150155353 - Fan; Su Chen ; et al.	2015-06-04
Middle of-line borderless contact structure and method of forming Grant 9,048,217 - Anderson , et al. June 2, 2	2015-06-02
Borderless contact for ultra-thin body devices Grant 9,024,389 - Fan , et al. May 5, 2	2015-05-05
Non-lithographic line pattern formation Grant 8,969,213 - Tseng , et al. March 3, 2	2015-03-03
Formation of the dielectric cap layer for a replacement gate structure Grant 8,957,465 - Xie , et al. February 17, 2	2015-02-17
Profile Control In Interconnect Structures App 20150035154 - Chen; Shyng-Tsong ; et al.	2015-02-05
Middle-of-line Borderless Contact Structure And Method Of Forming App 20150035026 - Anderson; Brent A. ; et al.	2015-02-05
Spacer For Enhancing Via Pattern Overlay Tolerence App 20150035157 - Holmes; Steven J. ; et al.	2015-02-05
Replacement gate MOSFET with raised source and drain Grant 8,946,006 - Ponoth , et al. February 3, 2	2015-02-03
Microelectronic substrate having removable edge extension element Grant 8,946,866 - Koburger, III , et al. February 3, 2	2015-02-03
Dual-metal self-aligned wires and vias Grant 8,946,908 - Holmes , et al. February 3, 2	2015-02-03
Finfets and fin isolation structures Grant 8,941,179 - Bergendahl , et al. January 27, 2	2015-01-27
Contact formation for ultra-scaled devices Grant 8,937,359 - Xie , et al. January 20, 2	2015-01-20
Integrated Circuit Structure Having Selectively Formed Metal Cap App 20150008527 - Yang; Chih-Chao ; et al.	2015-01-08
Dual hard mask lithography process Grant 8,916,337 - Arnold , et al. December 23, 2	2014-12-23
Middle of-line borderless contact structure and method of forming Grant 8,912,059 - Anderson , et al. December 16, 2	2014-12-16
Electrical fuse structure and method of fabricating same Grant 8,912,627 - Yang , et al. December 16, 2	2014-12-16
Replacement Gate Electrode With A Self-aligned Dielectric Spacer App 20140363941 - Ponoth; Shom ; et al.	2014-12-11
Single fin cut employing angled processing methods Grant 8,906,807 - Bergendahl , et al. December 9, 2	2014-12-09
Borderless contact for an aluminum-containing gate Grant 8,906,793 - Kanakasabapathy , et al. December 9, 2	2014-12-09
Creation of vias and trenches with different depths Grant 8,907,458 - Ponoth , et al. December 9, 2	2014-12-09
Hybrid copper interconnect structure and method of fabricating same Grant 8,901,744 - Yang , et al. December 2, 2	2014-12-02
Non-lithographic Line Pattern Formation App 20140349088 - Tseng; Chiahsun ; et al.	2014-11-27
Non-lithographic Hole Pattern Formation App 20140346640 - Tseng; Chiahsun ; et al.	2014-11-27
Dual Damascene Dual Alignment Interconnect Scheme App 20140342549 - Holmes; Steven J. ; et al.	2014-11-20
Contact Formation For Ultra-scaled Devices App 20140339629 - Xie; Ruilong ; et al.	2014-11-20
Methods of manufacturing finFET devices Grant 8,877,615 - Basker , et al. November 4, 2	2014-11-04
Integrated circuit structure having selectively formed metal cap Grant 8,877,645 - Yang , et al. November 4, 2	2014-11-04
Sealed air gap for semiconductor chip Grant 8,871,624 - Horak , et al. October 28, 2	2014-10-28
Formation Of The Dielectric Cap Layer For A Replacement Gate Structure App 20140299924 - XIE; Ruilong ; et al.	2014-10-09
Self-aligned contacts Grant 8,853,076 - Fan , et al. October 7, 2	2014-10-07
finFET devices Grant 8,847,323 - Basker , et al. September 30, 2	2014-09-30
Copper Interconnect Structures And Methods Of Making Same App 20140264878 - Yang; Chih-Chao ; et al.	2014-09-18
Replacement Gate Electrode With A Self-aligned Dielectric Spacer App 20140264490 - Ponoth; Shom ; et al.	2014-09-18
Method of fabricating a profile control in interconnect structures Grant 8,835,305 - Yang , et al. September 16, 2	2014-09-16
Electrical isolation structures for ultra-thin semiconductor-on-insulator devices Grant 8,836,031 - Haran , et al. September 16, 2	2014-09-16
Dual mandrel sidewall image transfer processes Grant 8,828,876 - Horak , et al. September 9, 2	2014-09-09
Air-dielectric for subtractive etch line and via metallization Grant 8,828,862 - Horak , et al. September 9, 2	2014-09-09
Finfets And Fin Isolation Structures App 20140231918 - Bergendahl; Marc A. ; et al.	2014-08-21
Copper interconnect structures and methods of making same Grant 8,802,558 - Yang , et al. August 12, 2	2014-08-12
Dual damascene dual alignment interconnect scheme Grant 8,803,321 - Holmes , et al. August 12, 2	2014-08-12
Borderless contact structure employing dual etch stop layers Grant 8,796,783 - Fan , et al. August 5, 2	2014-08-05
Air-dielectric For Subtractive Etch Line And Via Metallization App 20140203453 - Horak; David V. ; et al.	2014-07-24
FinFETs and fin isolation structures Grant 8,785,284 - Bergendahl , et al. July 22, 2	2014-07-22
Semiconductor structure containing an aluminum-containing replacement gate electrode Grant 8,779,515 - Kanakasabapathy , et al. July 15, 2	2014-07-15
Dual Mandrel Sidewall Image Transfer Processes App 20140190935 - Horak; David V. ; et al.	2014-07-10
Formation of the dielectric cap layer for a replacement gate structure Grant 8,772,168 - Xie , et al. July 8, 2	2014-07-08
Method of forming a borderless contact structure employing dual etch stop layers Grant 8,765,585 - Fan , et al. July 1, 2	2014-07-01
Formation of air gap with protection of metal lines Grant 8,754,520 - Nogami , et al. June 17, 2	2014-06-17
Low-profile local interconnect and method of making the same Grant 8,754,483 - Ponoth , et al. June 17, 2	2014-06-17
Recessing And Capping Of Gate Structures With Varying Metal Compositions App 20140159169 - XIE; Ruilong ; et al.	2014-06-12
Borderless contacts in semiconductor devices Grant 8,741,752 - Fan , et al. June 3, 2	2014-06-03
Air-dielectric for subtractive etch line and via metallization Grant 8,735,279 - Horak , et al. May 27, 2	2014-05-27
Copper Interconnect Structures And Methods Of Making Same App 20140124933 - Yang; Chih-Chao ; et al.	2014-05-08
Metal alloy cap integration Grant 8,716,127 - Yang , et al. May 6, 2	2014-05-06
Sub-lithographic Semiconductor Structures With Non-constant Pitch App 20140110817 - Bergendahl; Marc A. ; et al.	2014-04-24
Dual Hard Mask Lithography Process App 20140110846 - Arnold; John C. ; et al.	2014-04-24
Creation of vias and trenches with different depths Grant 8,703,604 - Ponoth , et al. April 22, 2	2014-04-22
Borderless interconnect line structure self-aligned to upper and lower level contact vias Grant 8,704,343 - Ponoth , et al. April 22, 2	2014-04-22
Microelectronic structure by selective deposition Grant 8,697,561 - Furukawa , et al. April 15, 2	2014-04-15
Single Fin Cut Employing Angled Processing Methods App 20140099792 - Bergendahl; Marc A. ; et al.	2014-04-10
Recessing and capping of gate structures with varying metal compositions Grant 8,679,909 - Xie , et al. March 25, 2	2014-03-25
Method to improve wet etch budget in FEOL integration Grant 8,679,941 - Cummings , et al. March 25, 2	2014-03-25
Middle-of-line Borderless Contact Structure And Method Of Forming App 20140077276 - Anderson; Brent A. ; et al.	2014-03-20
Self-aligned Contacts App 20140070282 - Fan; Su Chen ; et al.	2014-03-13
Overlay-tolerant Via Mask And Reactive Ion Etch (rie) Technique App 20140061930 - Holmes; Steven J. ; et al.	2014-03-06
Silicon-on-insulator Transistor With Self-aligned Borderless Source/drain Contacts App 20140061799 - FAN; Susan S. ; et al.	2014-03-06
Size-filtered Multimetal Structures App 20140065813 - Horak; David V. ; et al.	2014-03-06
Electrical Isolation Structures For Ultra-thin Semiconductor-on-insulator Devices App 20140061800 - Haran; Balasubramanian S. ; et al.	2014-03-06
Interconnect Structures And Methods For Back End Of The Line Integration App 20140068541 - HORAK; David V. ; et al.	2014-03-06
Profile Control In Interconnect Structures App 20140035142 - Yang; Chih-Chao ; et al.	2014-02-06
Non-lithographic Line Pattern Formation App 20140027917 - Tseng; Chiahsun ; et al.	2014-01-30
Non-lithographic Hole Pattern Formation App 20140027923 - Tseng; Chiahsun ; et al.	2014-01-30
Borderless contacts in semiconductor devices Grant 8,637,908 - Fan , et al. January 28, 2	2014-01-28
Interconnect structures and methods for back end of the line integration Grant 8,637,400 - Horak , et al. January 28, 2	2014-01-28
Electrical isolation structures for ultra-thin semiconductor-on-insulator devices Grant 8,629,008 - Haran , et al. January 14, 2	2014-01-14
Mask free protection of work function material portions in wide replacement gate electrodes Grant 8,629,511 - Koburger, III , et al. January 14, 2	2014-01-14
Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts Grant 8,623,730 - Fan , et al. January 7, 2	2014-01-07
Electrical fuse structure and method of fabricating same Grant 8,609,534 - Yang , et al. December 17, 2	2013-12-17
Recessing And Capping Of Gate Structures With Varying Metal Compositions App 20130328111 - Xie; Ruilong ; et al.	2013-12-12
Dual Damascene Dual Alignment Interconnect Scheme App 20130328208 - Holmes; Steven J. ; et al.	2013-12-12
Borderless Contacts For Metal Gates Through Selective Cap Deposition App 20130320414 - Fan; Su-Chen ; et al.	2013-12-05
Dual-metal Self-aligned Wires And Vias App 20130320546 - Holmes; Steven J. ; et al.	2013-12-05
Borderless Contacts For Metal Gates Through Selective Cap Deposition App 20130320411 - Fan; Su-Chen ; et al.	2013-12-05
Hybrid Copper Interconnect Structure And Method Of Fabricating Same App 20130320545 - Yang; Chih-Chao ; et al.	2013-12-05
Spacer For Enhancing Via Pattern Overlay Tolerence App 20130313717 - Holmes; Steven J. ; et al.	2013-11-28
Mask Free Protection Of Work Function Material Portions In Wide Replacement Gate Electrodes App 20130307086 - Koburger, III; Charles W. ; et al.	2013-11-21
Mask Free Protection Of Work Function Material Portions In Wide Replacement Gate Electrodes App 20130309857 - Koburger, III; Charles W. ; et al.	2013-11-21
Borderless Contact For An Aluminum-Containing Gate App 20130307033 - KANAKASABAPATHY; Sivananda K. ; et al.	2013-11-21
Borderless Contact For An Aluminum-containing Gate App 20130309852 - KANAKASABAPATHY; Sivananda K. ; et al.	2013-11-21
Dual-metal self-aligned wires and vias Grant 8,569,168 - Holmes , et al. October 29, 2	2013-10-29
CMOS gate structures fabricated by selective oxidation Grant 8,568,604 - Doris , et al. October 29, 2	2013-10-29
Integrated circuit line with electromigration barriers Grant 8,558,284 - Horak , et al. October 15, 2	2013-10-15
Metal Alloy Cap Integration App 20130252419 - Yang; Chih-Chao ; et al.	2013-09-26
Field effect transistor Grant 8,541,823 - Furukawa , et al. September 24, 2	2013-09-24
Hybrid copper interconnect structure and method of fabricating same Grant 8,525,339 - Yang , et al. September 3, 2	2013-09-03
Dual Hard Mask Lithography Process App 20130216776 - Arnold; John C. ; et al.	2013-08-22
Chemical and particulate filters containing chemically modified carbon nanotube structures Grant 8,512,458 - Holmes , et al. August 20, 2	2013-08-20
Dual-metal Self-aligned Wires And Vias App 20130207270 - Holmes; Steven J. ; et al.	2013-08-15
Multi-exposure lithography employing a single anti-reflective coating layer Grant 8,507,187 - Basker , et al. August 13, 2	2013-08-13
Structure For Nano-scale Metallization And Method For Fabricating Same App 20130193579 - Ponoth; Shom ; et al.	2013-08-01
Formation Of The Dielectric Cap Layer For A Replacement Gate Structure App 20130187203 - XIE; Ruilong ; et al.	2013-07-25
Metal alloy cap integration Grant 8,492,274 - Yang , et al. July 23, 2	2013-07-23
Pad bonding employing a self-aligned plated liner for adhesion enhancement Grant 8,492,265 - Yang , et al. July 23, 2	2013-07-23
Structure for nano-scale metallization and method for fabricating same Grant 8,492,270 - Ponoth , et al. July 23, 2	2013-07-23
Borderless Contact Structure App 20130181261 - BASKER; VEERARAGHAVAN S. ; et al.	2013-07-18
Electrical Isolation Structures For Ultra-thin Semiconductor-on-insulator Devices App 20130175622 - Haran; Balasubramanian S. ; et al.	2013-07-11
Silicon-on-insulator Transistor With Self-aligned Borderless Source/drain Contacts App 20130175619 - FAN; Susan S. ; et al.	2013-07-11
Method For Fabricating Silicon-on-insulator Transistor With Self-aligned Borderless Source/drain Contacts App 20130178052 - FAN; Susan S. ; et al.	2013-07-11
Pad bonding employing a self-aligned plated liner for adhesion enhancement Grant 8,482,132 - Yang , et al. July 9, 2	2013-07-09
Borderless Contact Structure Employing Dual Etch Stop Layers App 20130168749 - Fan; Su C. ; et al.	2013-07-04
Electrical Fuse Structure And Method Of Fabricating Same App 20130168806 - Yang; Chih-Chao ; et al.	2013-07-04
Sublithographic patterning employing image transfer of a controllably damaged dielectric sidewall Grant 8,476,160 - Ponoth , et al. July 2, 2	2013-07-02
Replacement Gate Mosfet With Raised Source And Drain App 20130161697 - Ponoth; Shom ; et al.	2013-06-27
Formation Of Air Gap With Protection Of Metal Lines App 20130134590 - Nogami; Takeshi ; et al.	2013-05-30
Borderless Contact For Ultra-thin Body Devices App 20130134517 - Fan; Su Chen ; et al.	2013-05-30
Sealed Air Gap For Semiconductor Chip App 20130130489 - Horak; David V. ; et al.	2013-05-23
Metal Alloy Cap Integration App 20130115767 - Yang; Chih-Chao ; et al.	2013-05-09
Metal Alloy Cap Integration App 20130112462 - Yang; Chih-Chao ; et al.	2013-05-09
Structure and method for manufacturing interconnect structures having self-aligned dielectric caps Grant 8,404,582 - Horak , et al. March 26, 2	2013-03-26
Integrated Circuit Structure Having Selectively Formed Metal Cap App 20130069161 - Yang; Chih-Chao ; et al.	2013-03-21
Formation of air gap with protection of metal lines Grant 8,399,350 - Nogami , et al. March 19, 2	2013-03-19
Sealed air gap for semiconductor chip Grant 8,390,079 - Horak , et al. March 5, 2	2013-03-05
Borderless contact for ultra-thin body devices Grant 8,383,490 - Fan , et al. February 26, 2	2013-02-26
Size-filtered Multimetal Structures App 20130043556 - Horak; David V. ; et al.	2013-02-21
FinFET devices Grant 8,368,146 - Basker , et al. February 5, 2	2013-02-05
Borderless Contact For Ultra-thin Body Devices App 20130026570 - Fan; Su Chen ; et al.	2013-01-31
Hybrid Copper Interconnect Structure and Method of Fabricating Same App 20130026635 - Yang; Chih-Chao ; et al.	2013-01-31
Borderless Contacts in Semiconductor Devices App 20130023115 - Fan; Su Chen ; et al.	2013-01-24
Interconnect structure for electromigration enhancement Grant 8,354,751 - Horak , et al. January 15, 2	2013-01-15
Finfet Devices And Methods Of Manufacture App 20130009249 - BASKER; Veeraraghavan S. ; et al.	2013-01-10
Microelectronic Structure Including Air Gap App 20130009282 - Edelstein; Daniel C. ; et al.	2013-01-10
Microelectronic Structure Including Air Gap App 20130012017 - Edelstein; Daniel C. ; et al.	2013-01-10
Forming borderless contact for transistors in a replacement metal gate process Grant 8,349,674 - Ponoth , et al. January 8, 2	2013-01-08
Low-profile Local Interconnect And Method Of Making The Same App 20120326237 - Ponoth; Shom ; et al.	2012-12-27
Borderless Interconnect Line Structure Self-aligned To Upper And Lower Level Contact Vias App 20120329275 - Ponoth; Shom ; et al.	2012-12-27
Interconnect structures and methods for back end of the line integration App 20120329267 - Horak; David V. ; et al.	2012-12-27
Sidewall Image Transfer Process Employing A Cap Material Layer For A Metal Nitride Layer App 20120282779 - Arnold; John C. ; et al.	2012-11-08
Borderless Contact Structure Employing Dual Etch Stop Layers App 20120273848 - Fan; Su C. ; et al.	2012-11-01
Sidewall image transfer process employing a cap material layer for a metal nitride layer Grant 8,298,954 - Arnold , et al. October 30, 2	2012-10-30
Borderless interconnect line structure self-aligned to upper and lower level contact vias Grant 8,299,625 - Ponoth , et al. October 30, 2	2012-10-30
Microelectronic structure including air gap Grant 8,288,268 - Edelstein , et al. October 16, 2	2012-10-16
Forming Borderless Contact For Transistors In A Replacement Metal Gate Process App 20120248508 - Ponoth; Shom ; et al.	2012-10-04
Microelectronic Substrate Having Removable Edge Extension Element App 20120241913 - Koburger, III; Charles W. ; et al.	2012-09-27
Device component forming method with a trim step prior to sidewall image transfer (SIT) processing App 20120208356 - Furukawa; Toshiharu ; et al.	2012-08-16
Sealed Air Gap For Semiconductor Chip App 20120199886 - Horak; David V. ; et al.	2012-08-09
Method of forming borderless contact for transistor Grant 8,232,204 - Horak , et al. July 31, 2	2012-07-31
Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach Grant 8,232,618 - Breyta , et al. July 31, 2	2012-07-31
Method to improve wet etch budget in FEOL integration Grant 8,232,179 - Cummings , et al. July 31, 2	2012-07-31
Air-dielectric For Subtractive Etch Line And Via Metallization App 20120187566 - Horak; David V. ; et al.	2012-07-26
Pad Bonding Employing A Self-aligned Plated Liner For Adhesion Enhancement App 20120190187 - Yang; Chih-Chao ; et al.	2012-07-26
Methods Of Manufacturing Finfet Devices App 20120190179 - BASKER; Veeraraghavan S. ; et al.	2012-07-26
Creation of vias and trenches with different depths Grant 8,227,339 - Ponoth , et al. July 24, 2	2012-07-24
Method To Improve Wet Etch Budget In Feol Integration App 20120178236 - Cummings; Jason E. ; et al.	2012-07-12
Integrated Circuit Line With Electromigration Barriers App 20120175775 - Horak; David V. ; et al.	2012-07-12
Creation Of Vias And Trenches With Different Depths App 20120171859 - Ponoth; Shom ; et al.	2012-07-05
Integrated circuit line with electromigration barriers Grant 8,211,776 - Horak , et al. July 3, 2	2012-07-03
Creation Of Vias And Trenches With Different Depths App 20120153503 - Ponoth; Shom ; et al.	2012-06-21
Microelectronic substrate having removable edge extension element Grant 8,202,460 - Koburger, III , et al. June 19, 2	2012-06-19
Microelectronic Structure By Selective Deposition App 20120142182 - Furukawa; Toshiharu ; et al.	2012-06-07
Device component forming method with a trim step prior to sidewall image transfer (SIT) processing Grant 8,183,159 - Furukawa , et al. May 22, 2	2012-05-22
Sublithographic Patterning Employing Image Transfer Of A Controllably Damaged Dielectric Sidewall App 20120104619 - Ponoth; Shom ; et al.	2012-05-03
Sealed Air Gap For Semiconductor Chip App 20120104512 - Horak; David V. ; et al.	2012-05-03
Replacement Gate Mosfet With Raised Source And Drain App 20120104470 - Ponoth; Shom ; et al.	2012-05-03
Borderless Interconnect Line Structure Self-aligned To Upper And Lower Level Contact Vias App 20120086128 - Ponoth; Shom ; et al.	2012-04-12
Electrical Fuse Structure And Method Of Fabricating Same App 20120074520 - Yang; Chih-Chao ; et al.	2012-03-29
Structure For Nano-scale Metallization And Method For Fabricating Same App 20120068346 - PONOTH; SHOM ; et al.	2012-03-22
Microelectronic structure by selective deposition Grant 8,138,100 - Furukawa , et al. March 20, 2	2012-03-20
Method of forming self-aligned local interconnect and structure formed thereby Grant 8,124,525 - Koburger, III , et al. February 28, 2	2012-02-28
Semiconductor Structure Having A Contact-level Air Gap Within The Interlayer Dielectrics Above A Semiconductor Device And A Method Of Forming The Semiconductor Structure Using A Self-assembly Approach App 20120037962 - Breyta; Gregory ; et al.	2012-02-16
Method of forming replacement metal gate with borderless contact and structure thereof Grant 8,084,311 - Horak , et al. December 27, 2	2011-12-27
Finfet Devices And Methods Of Manufacture App 20110303983 - BASKER; Veeraraghavan S. ; et al.	2011-12-15
Structure And Method For Manufacturing Interconnect Structures Having Self-aligned Dielectric Caps App 20110272812 - HORAK; DAVID V. ; et al.	2011-11-10
Microelectronic Structure Including Air Gap App 20110266682 - Edelstein; Daniel C. ; et al.	2011-11-03
Field Effect Transistor App 20110266621 - Furukawa; Toshiharu ; et al.	2011-11-03
Method and system for controlling radical distribution Grant 8,038,834 - Funk , et al. October 18, 2	2011-10-18
Shared gate for conventional planar device and horizontal CNT Grant 8,039,334 - Furukawa , et al. October 18, 2	2011-10-18
Temporary etchable liner for forming air gap Grant 8,030,202 - Horak , et al. October 4, 2	2011-10-04
Programmable anti-fuse structure with DLC dielectric layer Grant 8,008,669 - Yang , et al. August 30, 2	2011-08-30
Field effect transistor Grant 8,004,024 - Furukawa , et al. August 23, 2	2011-08-23
Formation Of Air Gap With Protection Of Metal Lines App 20110193230 - Nogami; Takeshi ; et al.	2011-08-11
Integrated Circuit Line With Electromigration Barriers App 20110163450 - Horak; David V. ; et al.	2011-07-07
Pseudo hybrid structure for low K interconnect integration Grant 7,955,968 - Leung , et al. June 7, 2	2011-06-07
Sub-lithographic dimensioned air gap formation and related structure Grant 7,943,480 - Edelstein , et al. May 17, 2	2011-05-17
Integrated circuit with upstanding stylus Grant 7,943,919 - Horak , et al. May 17, 2	2011-05-17
Creation Of Vias And Trenches With Different Depths App 20110101538 - Ponoth; Shom ; et al.	2011-05-05
Phase change memory cell with vertical transistor Grant 7,932,167 - Furukawa , et al. April 26, 2	2011-04-26
Carbon nanotube conductor for trench capacitors Grant 7,932,549 - Holmes , et al. April 26, 2	2011-04-26
Interconnect structure Grant 7,928,570 - Ponoth , et al. April 19, 2	2011-04-19
Phase change tip storage cell Grant 7,928,420 - Horak , et al. April 19, 2	2011-04-19
Integrated circuit with upstanding stylus Grant 7,928,012 - Horak , et al. April 19, 2	2011-04-19
Pad Bonding Employing A Self-aligned Plated Liner For Adhesion Enhancement App 20110084403 - Yang; Chih-Chao ; et al.	2011-04-14
Chemical and particulate filters containing chemically modified carbon nanotube structures Grant 7,922,796 - Holmes , et al. April 12, 2	2011-04-12
Method To Improve Wet Etch Budget In Feol Integration App 20110081765 - Cummings; Jason E. ; et al.	2011-04-07
Via gouging methods and related semiconductor structure Grant 7,892,968 - Chen , et al. February 22, 2	2011-02-22
Immersion lithography with equalized pressure on at least projection optics component and wafer Grant 7,889,317 - Furukawa , et al. February 15, 2	2011-02-15
Shared Gate For Conventional Planar Device And Horizontal Cnt App 20110027951 - Furukawa; Toshiharu ; et al.	2011-02-03
Programmable Anti-fuse Structure With Dlc Dielectric Layer App 20110018093 - Yang; Chih-Chao ; et al.	2011-01-27
Conductive liner at an interface between a shallow trench isolation structure and a buried oxide layer Grant 7,855,428 - Dennard , et al. December 21, 2	2010-12-21
Shared gate for conventional planar device and horizontal CNT Grant 7,838,943 - Furukawa , et al. November 23, 2	2010-11-23
Simultaneous conditioning of a plurality of memory cells through series resistors Grant 7,834,384 - Furukawa , et al. November 16, 2	2010-11-16
Layout and process to contact sub-lithographic structures Grant 7,825,525 - Furukawa , et al. November 2, 2	2010-11-02
Interconnect Structure App 20100264543 - Ponoth; Shom ; et al.	2010-10-21
Microelectronic structure by selective deposition Grant 7,816,743 - Furukawa , et al. October 19, 2	2010-10-19
Method of making integrated circuit (IC) including at least one storage cell Grant 7,795,068 - Horak , et al. September 14, 2	2010-09-14
Pseudo Hybrid Structure for Low K Interconnect Integration App 20100227471 - Leung; Pak K. ; et al.	2010-09-09
Reduced mask count gate conductor definition Grant 7,771,604 - Furukawa , et al. August 10, 2	2010-08-10
Method And System For Controlling Radical Distribution App 20100193471 - FUNK; Merritt ; et al.	2010-08-05
Method and system for controlling radical distribution Grant 7,718,030 - Funk , et al. May 18, 2	2010-05-18
Chemical And Particulate Filters Containing Chemically Modified Carbon Nanotube Structures App 20100119422 - Holmes; Steven J. ; et al.	2010-05-13
Chemical and particulate filters containing chemically modified carbon nanotube structures Grant 7,708,816 - Holmes , et al. May 4, 2	2010-05-04
Method for fabricating semiconductor device having conductive liner for rad hard total dose immunity Grant 7,704,854 - Dennard , et al. April 27, 2	2010-04-27
Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same Grant 7,687,877 - Yang , et al. March 30, 2	2010-03-30
Exposures system including chemical and particulate filters containing chemically modified carbon nanotube structures Grant 7,674,324 - Holmes , et al. March 9, 2	2010-03-09
Methods and structure for forming self-aligned borderless contacts for strain engineered logic devices Grant 7,659,171 - Furukawa , et al. February 9, 2	2010-02-09
Shallow trench isolation formation Grant 7,652,334 - Furukawa , et al. January 26, 2	2010-01-26
Method and apparatus for cleaning a semiconductor substrate in an immersion lithography system Grant 7,648,819 - Holmes , et al. January 19, 2	2010-01-19
Multi-exposure Lithography Employing A Single Anti-reflective Coating Layer App 20100009131 - Basker; Veeraraghavan S. ; et al.	2010-01-14
VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC App 20090321833 - Basker; Veeraraghaven S. ; et al.	2009-12-31
Interconnect Structure for Electromigration Enhancement App 20090309226 - Horak; David V. ; et al.	2009-12-17
Integrated Circuit With Upstanding Stylus App 20090305508 - HORAK; DAVID V. ; et al.	2009-12-10
Method For Fabricating Semiconductor Device Having Conductive Liner For Rad Hard Total Dose Immunity App 20090280619 - Dennard; Robert H. ; et al.	2009-11-12
Structure For Conductive Liner For Rad Hard Total Dose Immunity And Structure Thereof App 20090278226 - DENNARD; Robert H. ; et al.	2009-11-12
Interconnect Structure With A Mushroom-shaped Oxide Capping Layer And Method For Fabricating Same App 20090278258 - Yang; Chih-Chao ; et al.	2009-11-12
Carbon nanotubes as low voltage field emission sources for particle precipitators Grant 7,601,205 - Furukawa , et al. October 13, 2	2009-10-13
Sub-lithographic imaging techniques and processes Grant 7,585,614 - Furukawa , et al. September 8, 2	2009-09-08
Sub-lithographic Dimensioned Air Gap Formation And Related Structure App 20090200636 - Edelstein; Daniel C. ; et al.	2009-08-13
Via Gouging Methods And Related Semiconductor Structure App 20090184400 - Chen; Shyng-Tsong ; et al.	2009-07-23
Implantation of gate regions in semiconductor device fabrication Grant 7,557,023 - Furukawa , et al. July 7, 2	2009-07-07
Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells Grant 7,541,608 - Furukawa , et al. June 2, 2	2009-06-02
Vertical carbon nanotube transistor integration Grant 7,535,016 - Furukawa , et al. May 19, 2	2009-05-19
Field Effect Transistor App 20090121298 - Furukawa; Toshiharu ; et al.	2009-05-14
Accessible chip stack and process of manufacturing thereof Grant 7,528,494 - Furukawa , et al. May 5, 2	2009-05-05
Method And Apparatus For Cleaning A Semiconductor Substrate In An Immersion Lithography System App 20090087795 - Holmes; Steven J. ; et al.	2009-04-02
Microelectronic Structure By Selective Deposition App 20090072317 - Furukawa; Toshiharu ; et al.	2009-03-19
Microelectronic Structure By Selective Deposition App 20090075439 - Furukawa; Toshiharu ; et al.	2009-03-19
Methods For Forming Self-aligned Borderless Contacts For Strain Engineered Logic Devices And Structure Thereof App 20090057730 - Furukawa; Toshiharu ; et al.	2009-03-05
Conductive Element Forming Using Sacrificial Layer Patterned To Form Dielectric Layer App 20090032491 - Basker; Veeraraghavan S. ; et al.	2009-02-05
Carbon Nanotube Conductor For Trench Capacitors App 20090014767 - Furukawa; Toshiharu ; et al.	2009-01-15
Phase Change Memory Cell with Vertical Transistor App 20090001337 - Furukawa; Toshiharu ; et al.	2009-01-01
Chemical And Particulate Filters Containing Chemically Modified Carbon Nanotube Structures App 20080286466 - Holmes; Steven J. ; et al.	2008-11-20
Exposures System Including Chemical And Particulate Filters Containing Chemically Modified Carbon Nanotube Structures App 20080284992 - Holmes; Steven J. ; et al.	2008-11-20
Chemical And Particulate Filters Containing Chemically Modified Carbon Nanotube Structures App 20080282893 - Holmes; Steven J. ; et al.	2008-11-20
CMOS Gate Structures Fabricated by Selective Oxidation App 20080286971 - Doris; Bruce B. ; et al.	2008-11-20
Chemical And Particulate Filters Containing Chemically Modified Carbon Nanotube Structures App 20080271606 - Holmes; Steven J. ; et al.	2008-11-06
Carbon Nanotubes As Low Voltage Field Emission Sources for Particle Precipitators App 20080257156 - Furukawa; Toshiharu ; et al.	2008-10-23
Method Of Making Integrated Circuit (ic) Including At Least One Storage Cell App 20080248624 - Horak; David V. ; et al.	2008-10-09
Methods Of Forming Gas Dielectric And Related Structure App 20080217730 - Furukawa; Toshiharu ; et al.	2008-09-11
Bipolar Transistor Using Selective Dielectric Deposition And Methods For Fabrication Thereof App 20080203536 - Furukawa; Toshiharu ; et al.	2008-08-28
Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors App 20080185652 - Furukawa; Toshijaru ; et al.	2008-08-07
Mandrel/trim Alignment In Sit Processing App 20080188080 - Furukawa; Toshiharu ; et al.	2008-08-07
Immersion Lithography With Equalized Pressure On At Least Projection Optics Component And Wafer App 20080165335 - Furukawa; Toshiharu ; et al.	2008-07-10
Layout And Process To Contact Sub-lithographic Structures App 20080142995 - Furukawa; Toshiharu ; et al.	2008-06-19
Semiconductor Devices With Buried Isolation Regions App 20080128811 - Furukawa; Toshiharu ; et al.	2008-06-05
Memory Device And Mehtod Of Manufacturing The Device By Simulataneously Conditioning Transition Metal Oxide Layers In A Plurality Of Memory Cells App 20080131995 - Furukawa; Toshijaru ; et al.	2008-06-05
Multiple Layer And Cyrstal Plane Orientation Semiconductor Substrate App 20080099844 - Furukawa; Toshiharu ; et al.	2008-05-01
Multiple Layer And Crystal Plane Orientation Semiconductor Substrate App 20080102566 - Furukawa; Toshiharu ; et al.	2008-05-01
Feature Dimension Deviation Correction System, Method And Program Product App 20080027577 - Horak; David V. ; et al.	2008-01-31
Shallow Trench Isolation Formation App 20080017932 - Furukawa; Toshiharu ; et al.	2008-01-24
Microelectronic Structure By Selective Deposition App 20080001225 - Furukawa; Toshiharu ; et al.	2008-01-03
Illumination Light In Immersion Lithography Stepper For Particle Or Bubble Detection App 20070296937 - Furukawa; Toshiharu ; et al.	2007-12-27
Method And Structure For Forming Self-planarizing Wiring Layers In Multilevel Electronic Devices App 20070290394 - Furukawa; Toshiharu ; et al.	2007-12-20
Borderless Contact Structures App 20070241412 - Furukawa; Toshiharu ; et al.	2007-10-18
Simultaneous conditioning of a plurality of memory cells through series resistors App 20070235811 - Furukawa; Toshijaru ; et al.	2007-10-11
Method Of Doping A Gate Electrode Of A Field Effect Transistor App 20070228429 - Furukawa; Toshiharu ; et al.	2007-10-04
Layout and process to contact sub-lithographic structures App 20070215874 - Furukawa; Toshiharu ; et al.	2007-09-20
Memory Device And Method Of Manufacturing The Device By Simultaneously Conditioning Transition Metal Oxide Layers In A Plurality Of Memory Cells App 20070212810 - Furukawa; Toshijaru ; et al.	2007-09-13
Formation Of A Disposable Spacer To Post Dope A Gate Conductor App 20070205472 - Horak; David V. ; et al.	2007-09-06
Wiring Paterns Formed By Selective Metal Plating App 20070207604 - Furukawa; Toshiharu ; et al.	2007-09-06
CMOS Gate Structures Fabricated By Selective Oxidation App 20070190713 - Doris; Bruce B. ; et al.	2007-08-16
Methods for forming uniform lithographic features App 20070166981 - Furukawa; Toshiharu ; et al.	2007-07-19
Implantation Of Gate Regions In Semiconductor Device Fabrication App 20070148935 - Furukawa; Toshiharu ; et al.	2007-06-28
Y-shaped Carbon Nanotubes As Afm Probe For Analyzing Substrates With Angled Topography App 20070125946 - Boye; Carol A. ; et al.	2007-06-07
Silicon-on-insulator (soi) Read Only Memory (rom) Array And Method Of Making A Soi Rom App 20070128813 - Furukawa; Toshiharu ; et al.	2007-06-07
Pattern Density Control Using Edge Printing Processes App 20070105319 - Furukawa; Toshiharu ; et al.	2007-05-10
Accessible chip stack and process of manufacturing thereof App 20070096263 - Furukawa; Toshiharu ; et al.	2007-05-03
Shrinking Contact Apertures Through LPD Oxide App 20070099416 - Furukawa; Toshiharu ; et al.	2007-05-03
Method and system for controlling radical distribution App 20070068625 - Funk; Merritt ; et al.	2007-03-29
Microelectronic Substrate Having Removable Edge Extension Element App 20070063392 - Koburger III; Charles W. ; et al.	2007-03-22
Mandrel/trim alignment in SIT processing App 20070059891 - Furukawa; Toshiharu ; et al.	2007-03-15

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