Hoppe; Bodo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hoppe; Bodo.The latest application filed is for "identifying security vulnerabilities using modeled attribute propagation".

Company Profile

7.18.17

Hoppe; Bodo - BOEBLINGEN DE
Hoppe; Bodo - Tamm DE
Hoppe; Bodo - Stuttgart DE
Hoppe; Bodo - Ingershein DE
Hoppe; Bodo - Ingersheim DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Identifying Security Vulnerabilities Using Modeled Attribute Propagation App 20220121752 - Pardini; Matthew Michael Garcia ; et al.	2022-04-21
Error Injection For Timing Margin Protection And Frequency Closure App 20210157963 - Carey; Sean Michael ; et al.	2021-05-27
Determine soft error resilience while verifying architectural compliance Grant 10,896,118 - Erez , et al. January 19, 2	2021-01-19
Ranking combinations of mutants, test cases and random seeds in mutation testing Grant 10,614,192 - Gou , et al.	2020-04-07
Measuring execution time of benchmark programs in a simulated environment Grant 10,437,699 - Eckmann , et al. O	2019-10-08
Measuring execution time of benchmark programs in a simulated environment Grant 10,430,311 - Eckmann , et al. O	2019-10-01
Determine Soft Error Resilience While Verifying Architectural Compliance App 20190227906 - Erez; Ophir ; et al.	2019-07-25
Determine soft error resilience while verifying architectural compliance Grant 10,318,406 - Erez , et al.	2019-06-11
Determine Soft Error Resilience While Verifying Architectural Compliance App 20180239691 - Erez; Ophir ; et al.	2018-08-23
Ranking Combinations Of Mutants, Test Cases And Random Seeds In Mutation Testing App 20180144090 - GOU; Peng Fei ; et al.	2018-05-24
Ranking combinations of mutants, test cases and random seeds in mutation testing Grant 9,965,580 - Gou , et al. May 8, 2	2018-05-08
Protecting chip settings using secured scan chains Grant 9,727,754 - Geukes , et al. August 8, 2	2017-08-08
Assuring chip reliability with automatic generation of drivers and assertions Grant 9,600,616 - Arbel , et al. March 21, 2	2017-03-21
Assuring chip reliability with automatic generation of drivers and assertions Grant 9,483,591 - Arbel , et al. November 1, 2	2016-11-01
Determining a quality parameter for a verification environment Grant 9,443,044 - Gou , et al. September 13, 2	2016-09-13
Measuring Execution Time Of Benchmark Programs In A Simulated Environment App 20160210214 - Eckmann; Sascha ; et al.	2016-07-21
Measuring Execution Time Of Benchmark Programs In A Simulated Environment App 20160210213 - Eckmann; Sascha ; et al.	2016-07-21
Protecting Chip Settings Using Secured Scan Chains App 20160070933 - Geukes; Benedikt ; et al.	2016-03-10
Ranking Combinations of Mutants, Test Cases and Random Seeds in Mutation Testing App 20150379187 - GOU; Peng Fei ; et al.	2015-12-31
Protecting chip settings using secured scan chains Grant 9,222,973 - Geukes , et al. December 29, 2	2015-12-29
Verifying processor-sparing functionality in a simulation environment Grant 9,098,653 - Letz , et al. August 4, 2	2015-08-04
Determining A Quality Parameter For A Verification Environment App 20150121323 - Gou; Peng Fei ; et al.	2015-04-30
Verifying processor-sparing functionality in a simulation environment Grant 9,015,025 - Letz , et al. April 21, 2	2015-04-21
Verifying Processor-sparing Functionality In A Simulation Environment App 20140074451 - Letz; Stefan ; et al.	2014-03-13
Verifying Processor-Sparing Functionality in a Simulation Environment App 20130110490 - Letz; Stefan ; et al.	2013-05-02
Protecting Chip Settings Using Secured Scan Chains App 20120191403 - Geukes; Benedikt ; et al.	2012-07-26
System for performing verification of logic circuits Grant 7,565,636 - Hoppe , et al. July 21, 2	2009-07-21
System for Performing Verification of Logic Circuits App 20080216030 - Hoppe; Bodo ; et al.	2008-09-04
Method for performing verification of logic circuits Grant 7,398,494 - Hoppe , et al. July 8, 2	2008-07-08
Method for verification of gate level netlists using colored bits Grant 7,213,220 - Hoppe , et al. May 1, 2	2007-05-01
Method and System for Performing Verification of Logic Circuits App 20070050739 - Hoppe; Bodo ; et al.	2007-03-01
Method for verification of gate level netlisits using colored bits App 20050138586 - Hoppe, Bodo ; et al.	2005-06-23

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