| Patent | Date |
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Integrated circuit memory having a read circuit
Grant 7,499,344 - Nirschl , et al. March 3, 2 | 2009-03-03 |
Read circuit for resistive memory
App 20070153569 - Nirschl; Thomas ; et al. | 2007-07-05 |
Random access semiconductor memory with reduced signal overcoupling
Grant 6,826,075 - Gogl , et al. November 30, 2 | 2004-11-30 |
Magnetic memory configuration
Grant 6,816,406 - Honigschmid , et al. November 9, 2 | 2004-11-09 |
MRAM configuration having selection transistors with a large channel width
Grant 6,803,618 - Honigschmid , et al. October 12, 2 | 2004-10-12 |
Magnetic memory configuration
App 20040100836 - Honigschmid, Heinz ; et al. | 2004-05-27 |
Data memory with a plurality of memory banks
Grant 6,741,513 - Honigschmid , et al. May 25, 2 | 2004-05-25 |
Ferroelectric memory configuration and a method for producing the configuration
Grant 6,664,158 - Dehm , et al. December 16, 2 | 2003-12-16 |
Integrated memory with memory cell array
Grant 6,657,916 - Honigschmid , et al. December 2, 2 | 2003-12-02 |
MRAM configuration having selection transistors with a large channel width
App 20030218926 - Honigschmid, Heinz ; et al. | 2003-11-27 |
Process for producing a capacitor configuration
Grant 6,645,809 - Honigschmid , et al. November 11, 2 | 2003-11-11 |
Integrated memory having memory cells and reference cells, and operating method for such a memory
Grant 6,487,128 - Bohm , et al. November 26, 2 | 2002-11-26 |
Ferroelectric memory configuration and a method for producing the configuration
App 20020123203 - Dehm, Christine ; et al. | 2002-09-05 |
Integrated memory
App 20020116591 - Honigschmid, Heinz ; et al. | 2002-08-22 |
Data memory with a plurality of memory banks
App 20020114206 - Honigschmid, Heinz ; et al. | 2002-08-22 |
MRAM memory cell
Grant 6,424,563 - Honigschmid July 23, 2 | 2002-07-23 |
Circuit configuration for controlling write and read operations in a magnetoresistive memory configuration
App 20020080661 - Gogl, Dietmar ; et al. | 2002-06-27 |
Process for producing a capacitor configuration
App 20020081790 - Honigschmid, Heinz ; et al. | 2002-06-27 |
Integrated memory having memory cells and reference cells, and corresponding operating method
App 20020071317 - Bohm, Thomas ; et al. | 2002-06-13 |
Integrated Ferroelectric Memory Having Plate Lines Selected By A Column Decoder
App 20020054501 - Honigschmid, Heinz ; et al. | 2002-05-09 |
Circuit configuration and method for accelerating aging in an MRAM
App 20020050840 - Honigschmid, Heinz | 2002-05-02 |
Integrated memory and corresponding operating method
App 20020044493 - Bohm, Thomas ; et al. | 2002-04-18 |
Integrated memory having memory cells that each include a ferroelectric memory transistor
App 20020044478 - Honigschmid, Heinz ; et al. | 2002-04-18 |
Integrated memory having memory cells and reference cells, and operating method for such a memory
App 20020027816 - Bohm, Thomas ; et al. | 2002-03-07 |
Integrated semiconductor memory with redundant units for memory cells
Grant 6,353,562 - Bohm , et al. March 5, 2 | 2002-03-05 |
Circuit configuration for reading a memory cell having a ferroelectric capacitor
App 20020024836 - Braun, Georg ; et al. | 2002-02-28 |
Integrated memory having a differential sense amplifier
Grant 6,351,422 - Rohr , et al. February 26, 2 | 2002-02-26 |
Integrated memory with redundancy
App 20020015337 - Neuhold, Ernst ; et al. | 2002-02-07 |
Random access semiconductor memory with reduced signal overcoupling
App 20020012266 - Gogl, Dietmar ; et al. | 2002-01-31 |
MRAM memory cell
App 20020008989 - Honigschmid, Heinz | 2002-01-24 |
Decoder element for generating an output signal having three different potentials and an operating method for the decoder element
App 20020008564 - Bohm, Thomas ; et al. | 2002-01-24 |
Integrated memory with redundancy and method for repairing an integrated memory
App 20020003728 - Honigschmid, Heinz ; et al. | 2002-01-10 |
Integrated memory
App 20020003735 - Bohm, Thomas ; et al. | 2002-01-10 |
Fuse circuit configuration
App 20010054948 - Honigschmid, Heinz | 2001-12-27 |
Integrated memory having a differential sense amplifier
App 20010038562 - Rohr, Thomas ; et al. | 2001-11-08 |
Circuit configuration for generating a reference voltage for reading a ferroelectric memory
App 20010038557 - Braun, Georg ; et al. | 2001-11-08 |
Integrated semiconductor memory having memory cells with a ferroelectric memory property
App 20010038561 - Esterl, Robert ; et al. | 2001-11-08 |
Method for operating a ferroelectric memory configuration and a ferroelectric memory configuration
App 20010036099 - Honigschmid, Heinz ; et al. | 2001-11-01 |
Method for operating an integrated memory
App 20010036100 - Esterl, Robert ; et al. | 2001-11-01 |
Integrated memory with plate line segments
App 20010030894 - Braun, Georg ; et al. | 2001-10-18 |
Semiconductor circuit configuration
App 20010028090 - Braun, Georg ; et al. | 2001-10-11 |
Semiconductor memory configuration with a refresh logic circuit, and method of refreshing a memory content of the semiconductor memory configuration
App 20010026491 - Bohm, Thomas ; et al. | 2001-10-04 |
Decoder element for producing an output signal having three different potentials
App 20010026485 - Rohr, Thomas ; et al. | 2001-10-04 |
Integrated semiconductor memory with redundant units for memory cells
App 20010021134 - Bohm, Thomas ; et al. | 2001-09-13 |
Ferroelectric memory array
App 20010012213 - Braun, Georg ; et al. | 2001-08-09 |
Ferroelectric memory and method for preventing aging in a memory cell
Grant 6,091,625 - Braun , et al. July 18, 2 | 2000-07-18 |
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