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Patent applications and USPTO patent grants for Hong; Weilun.The latest application filed is for "gate height loss improvement for a transistor".
Patent | Date |
---|---|
Planarization process for semiconductor device fabrication Grant 8,975,179 - Tu , et al. March 10, 2 | 2015-03-10 |
Gate height loss improvement for a transistor Grant 8,598,028 - Tu , et al. December 3, 2 | 2013-12-03 |
Gate Height Loss Improvement For A Transistor App 20130164930 - Tu; Che-Hao ;   et al. | 2013-06-27 |
Planarization Process For Semiconductor Device Fabrication App 20130095644 - Tu; Che-Hao ;   et al. | 2013-04-18 |
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