loadpatents
name:-0.010742902755737
name:-0.12688398361206
name:-0.0016019344329834
Hong; Gary Patent Filings

Hong; Gary

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hong; Gary.The latest application filed is for "closed-loop distributed messaging system and method".

Company Profile
0.110.11
  • Hong; Gary - Markham CA
  • Hong; Gary - Hsinchu TW
  • Hong; Gary - Hsin-Chu TW
  • Hong; Gary - Hsinchu Hsien TW
  • Hong; Gary - Hsin TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Closed-loop distributed messaging system and method
App 20140114725 - Tryfon; Jason ;   et al.
2014-04-24
Closed-loop Distributed Messaging System And Method
App 20140046728 - Tryfon; Jason ;   et al.
2014-02-13
Method for operating a non-volatile memory
Grant 6,757,198 - Huang , et al. June 29, 2
2004-06-29
Method for measuring an effective channel length of a MOSFET
Grant 6,750,673 - Huang , et al. June 15, 2
2004-06-15
Method for forming a cantilever beam model micro-electromechanical system
Grant 6,720,267 - Chen , et al. April 13, 2
2004-04-13
Method for operating a non-volatile memory
App 20030142548 - Huang, Chih-Jen ;   et al.
2003-07-31
Method for operating a non-volatile memory
App 20030107921 - Huang, Chih-Jen ;   et al.
2003-06-12
Method of forming shallow trench isolation
App 20020182824 - Lin, Ying-Jen ;   et al.
2002-12-05
Method for measuring effective gate channel length during C-V method
App 20020102752 - Huang, Heng-Seng ;   et al.
2002-08-01
Method of manufacturing inductor
App 20020066175 - Huang, Heng-sheng ;   et al.
2002-06-06
Vertical two-transistor flash memory
Grant 6,396,745 - Hong , et al. May 28, 2
2002-05-28
Method for forming a self-aligned silicide layer
Grant 6,350,677 - Ko , et al. February 26, 2
2002-02-26
Self-aligned Metal Silicide
App 20020011631 - HONG, GARY
2002-01-31
Method For Fabricating A Hybrid Isolation Structure
App 20010023107 - HONG, GARY ;   et al.
2001-09-20
Method of fabricating conductive line structure
Grant 6,274,477 - Hong August 14, 2
2001-08-14
Method for manufacturing shallow trench isolation structure including a dual trench
Grant 6,232,202 - Hong May 15, 2
2001-05-15
Method of stabilizing anti-reflection coating layer
Grant 6,225,219 - Lee , et al. May 1, 2
2001-05-01
Method of fabricating an ETOX flash memory
Grant 6,211,012 - Lee , et al. April 3, 2
2001-04-03
Method of fabricating flash memory
Grant 6,153,471 - Lee , et al. November 28, 2
2000-11-28
Shallow trench isolation for semiconductor devices
Grant 6,069,058 - Hong May 30, 2
2000-05-30
Method for manufacturing dram capacitor incorporating liquid phase deposition
Grant 6,060,366 - Hong May 9, 2
2000-05-09
Method of manufacturing flash memory
Grant 6,048,768 - Ding , et al. April 11, 2
2000-04-11
Method of making high density mask ROM having a two level bit line
Grant 6,037,227 - Hong March 14, 2
2000-03-14
Method of fabricating capacitor
Grant 6,037,234 - Hong , et al. March 14, 2
2000-03-14
Method for forming shallow trench isolation structure
Grant 6,001,707 - Lin , et al. December 14, 1
1999-12-14
ROM device having shaped gate electrodes and corresponding code implants
Grant 5,994,745 - Hong November 30, 1
1999-11-30
Process for DRAM capacitor formation
Grant 5,976,977 - Hong November 2, 1
1999-11-02
Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile
Grant 5,972,752 - Hong October 26, 1
1999-10-26
Method of nitride-sealed oxide-buffered local oxidation of silicon
Grant 5,970,364 - Huang , et al. October 19, 1
1999-10-19
Flash memory having separate data programming and erasing terminals
Grant 5,969,384 - Hong October 19, 1
1999-10-19
DRAM process with a multilayer stack structure
Grant 5,966,600 - Hong October 12, 1
1999-10-12
Method of fabricating electrostatic discharge protection device
Grant 5,960,288 - Hong , et al. September 28, 1
1999-09-28
Method for manufacturing DRAM capacitor
Grant 5,952,039 - Hong September 14, 1
1999-09-14
Flash memory cell structure having electrically isolated stacked gate
Grant 5,932,910 - Hong August 3, 1
1999-08-03
DRAM process
Grant 5,902,124 - Hong May 11, 1
1999-05-11
Sub-micron MOSFET
Grant 5,899,719 - Hong May 4, 1
1999-05-04
Method of fabricating a flash memory
Grant 5,869,369 - Hong February 9, 1
1999-02-09
Planar field oxide isolation process for semiconductor integrated circuit devices using liquid phase deposition
Grant 5,849,625 - Hsue , et al. December 15, 1
1998-12-15
Deep submicron MOSFET device
Grant 5,843,826 - Hong December 1, 1
1998-12-01
Method of fabricating metal contact of ultra-large-scale integration metal-oxide semiconductor field effect transistor with silicon-on-insulator structure
Grant 5,726,081 - Lin , et al. March 10, 1
1998-03-10
High density flash EPROM
Grant 5,721,442 - Hong February 24, 1
1998-02-24
Method of fabricating a stacked capacitor for a DRAM cell by plasma etching
Grant 5,721,152 - Jenq , et al. February 24, 1
1998-02-24
Process for fabricating a stacked capacitor
Grant 5,716,884 - Hsue , et al. February 10, 1
1998-02-10
Method of forming isolation regions in a MOS transistor device
Grant 5,674,760 - Hong October 7, 1
1997-10-07
Method of forming bit lines having lower conductivity in their respective edges
Grant 5,672,532 - Hsue , et al. September 30, 1
1997-09-30
Process for creating high density integrated circuits utilizing double coating photoresist mask
Grant 5,667,940 - Hsue , et al. September 16, 1
1997-09-16
Method for fabricating trench/stacked capacitors on DRAM cells with increased capacitance
Grant 5,665,624 - Hong September 9, 1
1997-09-09
Mask ROM process with self-aligned ROM code implant
Grant 5,661,326 - Hong August 26, 1
1997-08-26
Method of bonding an aluminum wire to an intergrated circuit bond pad
Grant 5,661,081 - Hsue , et al. August 26, 1
1997-08-26
Process for fabricating non-volatile memory cells having improved voltage coupling ratio by utilizing liquid phase
Grant 5,646,059 - Sheu , et al. July 8, 1
1997-07-08
High-density programmable read-only memory and the process for its fabrication
Grant 5,643,816 - Hsu , et al. July 1, 1
1997-07-01
High performance field effect transistor with lai region
Grant 5,635,749 - Hong June 3, 1
1997-06-03
Method of manufacturing buried bit line flash EEPROM memory cell
Grant 5,635,415 - Hong June 3, 1
1997-06-03
Flash EEPROM memory cell with polysilicon source/drain
Grant 5,631,482 - Hong May 20, 1
1997-05-20
Flash memory array with self-limiting erase
Grant 5,625,600 - Hong April 29, 1
1997-04-29
Interconnection with self-aligned via plug
Grant 5,596,230 - Hong January 21, 1
1997-01-21
Method for manufacturing a stacked/trench DRAM capacitor
Grant 5,585,303 - Hong , et al. December 17, 1
1996-12-17
Double poly high density buried bit line mask ROM
Grant 5,578,857 - Hong , et al. November 26, 1
1996-11-26
Flash memory array with self-limiting erase
Grant 5,576,993 - Hong November 19, 1
1996-11-19
Flash memory cell with self-aligned tunnel dielectric area above LDD structure
Grant 5,569,946 - Hong October 29, 1
1996-10-29
Process for fabricating a flash EEPROM
Grant 5,556,799 - Hong September 17, 1
1996-09-17
Method for isolating non-volatile memory cells
Grant 5,556,798 - Hong September 17, 1
1996-09-17
Ion implanted programmable cell for read only memory applications
Grant 5,550,075 - Hsu , et al. August 27, 1
1996-08-27
Process for fabricating MOS transistors having full-overlap lightly-doped drain structure
Grant 5,538,913 - Hong July 23, 1
1996-07-23
Process for fabricating MOS LDD transistor with pocket implant
Grant 5,534,447 - Hong July 9, 1
1996-07-09
Method of making buried bit line ROM with low bit line resistance
Grant 5,529,943 - Hong , et al. June 25, 1
1996-06-25
Method for making doped well and field regions on semiconductor substrates for field effect transistors using liquid phase deposition of oxides
Grant 5,525,535 - Hong June 11, 1
1996-06-11
Method for fabricating a self aligned mask ROM
Grant 5,523,251 - Hong June 4, 1
1996-06-04
Method of manufacture of a split gate flash EEPROM memory cell
Grant 5,512,503 - Hong April 30, 1
1996-04-30
Process for post metal coding of a ROM, by gate etch
Grant 5,512,507 - Yang , et al. April 30, 1
1996-04-30
MOSFET device structure three spaced-apart deep boron implanted channel regions aligned with gate electrode of NMOSFET device
Grant 5,512,770 - Hong April 30, 1
1996-04-30
Buried bit line mask ROM process
Grant 5,510,288 - Hong April 23, 1
1996-04-23
Method of making a high resistance drain junction resistor in a SRAM
Grant 5,506,167 - Chen , et al. April 9, 1
1996-04-09
Method for fabricating semiconductor devices with localized pocket implantation
Grant 5,504,023 - Hong April 2, 1
1996-04-02
Method of fabricating thin O/N/O stacked dielectric for high-density DRAMs
Grant 5,504,021 - Hong , et al. April 2, 1
1996-04-02
Split-gate process for non-volatile memory
Grant 5,496,747 - Hong March 5, 1
1996-03-05
Split-gate flash memory cell
Grant 5,495,441 - Hong February 27, 1
1996-02-27
Method of forming a MOS device having a localized anti-punchthrough region
Grant 5,489,543 - Hong February 6, 1
1996-02-06
Trench EEPROM with tunnel oxide in trench
Grant 5,486,714 - Hong January 23, 1
1996-01-23
Method for fabricating a stacked capacitor for dynamic random access memory cell
Grant 5,484,744 - Hong January 16, 1
1996-01-16
Process of fabricating split gate flash memory cell
Grant 5,482,879 - Hong January 9, 1
1996-01-09
Structure for flash memory cell
Grant 5,481,128 - Hong January 2, 1
1996-01-02
Method of making a flash EEPROM memory cell comprising polysilicon and textured oxide sidewall spacers
Grant 5,478,767 - Hong December 26, 1
1995-12-26
High performance field effect transistor and method of manufacture thereof
Grant 5,478,763 - Hong December 26, 1
1995-12-26
Method for fabricating polycide gate MOSFET devices
Grant 5,472,896 - Chen , et al. December 5, 1
1995-12-05
Method for improving erase characteristics and coupling ratios of buried bit line flash EPROM devices
Grant 5,473,179 - Hong December 5, 1
1995-12-05
Method of fabricating lightly doped drain transistor device
Grant 5,472,894 - Hsu , et al. December 5, 1
1995-12-05
Method for fabricating MOS device with reduced anti-punchthrough region
Grant 5,472,897 - Hsu , et al. December 5, 1
1995-12-05
Method of making a flash EPROM device having a drain edge P+ implant
Grant 5,464,785 - Hong November 7, 1
1995-11-07
Method of making high coupling ratio flash EEPROM device
Grant 5,460,991 - Hong October 24, 1
1995-10-24
Process for high density flash EPROM cell
Grant 5,460,988 - Hong October 24, 1
1995-10-24
Method for making fin-shaped stack capacitors on DRAM chips
Grant 5,460,999 - Hong , et al. October 24, 1
1995-10-24
Method of making top floating-gate flash EEPROM structure
Grant 5,457,061 - Hong , et al. October 10, 1
1995-10-10
Lightly doped drain transistor device having the polysilicon sidewall spacers
Grant 5,453,635 - Hsu , et al. September 26, 1
1995-09-26
Process on thickness control for silicon-on-insulator technology
Grant 5,449,638 - Hong , et al. September 12, 1
1995-09-12
Method of manufacturing EEPROM memory device with a select gate
Grant 5,445,983 - Hong August 29, 1
1995-08-29
Method of making a split gate flash memory cell
Grant 5,445,984 - Hong , et al. August 29, 1
1995-08-29
Method of fabrication of MOSFET device with buried bit line
Grant 5,438,009 - Yang , et al. August 1, 1
1995-08-01
Manufacture of an asymmetric non-volatile memory cell
Grant 5,432,106 - Hong July 11, 1
1995-07-11
Process for EPROM, flash memory with high coupling ratio
Grant 5,432,112 - Hong July 11, 1
1995-07-11
Method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel
Grant 5,429,956 - Shell , et al. July 4, 1
1995-07-04
Method of making flash EEPROM memory
Grant 5,429,960 - Hong July 4, 1
1995-07-04
Process for producing a very high density mask ROM
Grant 5,429,967 - Hong July 4, 1
1995-07-04
Method of making flash EEPROM memory cell
Grant 5,429,970 - Hong July 4, 1
1995-07-04
Process for flat-cell mask ROM integrated circuit
Grant 5,418,175 - Hsue , et al. May 23, 1
1995-05-23
Method of making self-aligned MOSFET
Grant 5,413,949 - Hong May 9, 1
1995-05-09
Method of forming a DRAM stacked capacitor cell
Grant 5,413,950 - Chen , et al. May 9, 1
1995-05-09
Process for high density split-gate memory cell for flash or EPROM
Grant 5,414,287 - Hong May 9, 1
1995-05-09
Method of making flash memory cell with self-aligned tunnel dielectric area
Grant 5,413,946 - Hong May 9, 1
1995-05-09
Process of manufacture of split gate EPROM device
Grant 5,395,779 - Hong March 7, 1
1995-03-07
Process for fabricating double poly high density buried bit line mask ROM
Grant 5,393,233 - Hong , et al. February 28, 1
1995-02-28
Interconnection process with self-aligned via plug
Grant 5,382,545 - Hong January 17, 1
1995-01-17
Method of making a bottom gate mask ROM device
Grant 5,378,647 - Hong January 3, 1
1995-01-03
Method for improving erase characteristics and coupling ratios of buried bit line flash EPROM devices
Grant 5,352,619 - Hong October 4, 1
1994-10-04
Device for preventing antenna effect on circuit
Grant 5,350,710 - Hong , et al. September 27, 1
1994-09-27
Flash memory cell and its operation
Grant 5,349,220 - Hong September 20, 1
1994-09-20
Uniform field oxidation for locos isolation
Grant 5,308,787 - Hong , et al. May 3, 1
1994-05-03
Mask ROM process
Grant 5,308,777 - Hong May 3, 1
1994-05-03
Method of fabricating a flash memory cell
Grant 5,298,447 - Hong March 29, 1
1994-03-29

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