loadpatents
name:-0.003197193145752
name:-0.027795791625977
name:-0.00058507919311523
Holler; Mark A. Patent Filings

Holler; Mark A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Holler; Mark A..The latest application filed is for "method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time".

Company Profile
0.23.2
  • Holler; Mark A. - Palo Alto CA
  • Holler; Mark A. - Milpitas CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time
Grant 7,152,172 - Tsirkel , et al. December 19, 2
2006-12-19
Method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time
App 20040073827 - Tsirkel, Aaron M. ;   et al.
2004-04-15
Method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time
Grant 6,665,805 - Tsirkel , et al. December 16, 2
2003-12-16
Computer vision control variable transformation
Grant 6,538,649 - Bradski , et al. March 25, 2
2003-03-25
Computer Vision Control Variable Transformation
App 20010040572 - BRADSKI, GARY R. ;   et al.
2001-11-15
Distance calculating neural network classifier chip and system
Grant 5,487,133 - Park , et al. January 23, 1
1996-01-23
Method of increasing the accuracy of an analog circuit employing floating gate memory devices
Grant 5,268,320 - Holler , et al. December 7, 1
1993-12-07
Difference calculating neural network utilizing switched capacitors
Grant 5,264,734 - Holler , et al. November 23, 1
1993-11-23
Method of increasing the accuracy of an analog neural network and the like
Grant 5,146,602 - Holler , et al. September 8, 1
1992-09-08
Multi-layer neural network employing multiplexed output neurons
Grant 5,087,826 - Holler , et al. February 11, 1
1992-02-11
Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth
Grant 5,077,230 - Woo , et al. December 31, 1
1991-12-31
Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps
Grant 5,075,245 - Woo , et al. December 24, 1
1991-12-24
Semiconductor cell for neural network and the like
Grant 5,055,897 - Canepa , et al. October 8, 1
1991-10-08
Four quadrant synapse cell employing single column summing line
Grant 5,028,810 - Castro , et al. July 2, 1
1991-07-02
Synapse cell employing dual gate transistor structure
Grant 4,961,002 - Tam , et al. October 2, 1
1990-10-02
Adaptive synapse cell providing both excitatory and inhibitory connections in an associative network
Grant 4,956,564 - Holler , et al. September 11, 1
1990-09-11
Semiconductor cell for neural network employing a four-quadrant multiplier
Grant 4,950,917 - Holler , et al. August 21, 1
1990-08-21
Sample and hold circuit for temporal associations in a neural network
Grant 4,906,865 - Holler March 6, 1
1990-03-06
Source drain doping technique
Grant 4,784,965 - Woo , et al. November 15, 1
1988-11-15
Process for fabricating electrically alterable floating gate memory devices
Grant 4,780,424 - Holler , et al. October 25, 1
1988-10-25
Source drain doping technique
Grant 4,757,026 - Woo , et al. July 12, 1
1988-07-12
Method of fabricating a MOSFET with graded source and drain regions
Grant 4,728,617 - Woo , et al. March 1, 1
1988-03-01
Method of making EPROM cell with reduced programming voltage
Grant 4,519,849 - Korsh , et al. May 28, 1
1985-05-28
Virtual ground memory
Grant 4,460,981 - Van Buskirk , et al. July 17, 1
1984-07-17
EPROM Cell with reduced programming voltage and method of fabrication
Grant 4,412,310 - Korsh , et al. October 25, 1
1983-10-25

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