| Patent | Date |
|---|
Method and system for power signature suppression in memory devices
Grant 9,870,810 - Kurjanowicz , et al. January 16, 2 | 2018-01-16 |
Method And System For Power Signature Suppression In Memory Devices
App 20170337957 - KURJANOWICZ; Wlodek ; et al. | 2017-11-23 |
Performance characteristic monitoring circuit and method
Grant 9,404,966 - Dwivedi , et al. August 2, 2 | 2016-08-02 |
Post fabrication tuning of an integrated circuit
Grant 9,374,072 - Hold , et al. June 21, 2 | 2016-06-21 |
Controlling the voltage level on the word line to maintain performance and reduce access disturbs
Grant 9,105,315 - Hold , et al. August 11, 2 | 2015-08-11 |
Handling of write operations within a memory device
Grant 9,064,561 - Hold June 23, 2 | 2015-06-23 |
Memory device and a method of operating such a memory device in a speculative read mode
Grant 8,995,191 - Hold March 31, 2 | 2015-03-31 |
Techniques for providing a direct injection semiconductor memory device
Grant 8,947,965 - Van Buskirk , et al. February 3, 2 | 2015-02-03 |
Post Fabrication Tuning Of An Integrated Circuit
App 20140312956 - HOLD; Betina ; et al. | 2014-10-23 |
Post fabrication tuning of an integrated circuit
Grant 8,717,084 - Hold , et al. May 6, 2 | 2014-05-06 |
Controlling The Voltage Level On The Word Line To Maintain Performance And Reduce Access Disturbs
App 20140022835 - HOLD; Betina ; et al. | 2014-01-23 |
Memory Device And A Method Of Operating Such A Memory Device In A Speculative Read Mode
App 20140016419 - Hold; Betina | 2014-01-16 |
Performance Characteristic Monitoring Circuit And Method
App 20140015562 - Dwivedi; Sandeep ; et al. | 2014-01-16 |
Memory device and a method of operating such a memory device in a speculative read mode
Grant 8,599,626 - Hold December 3, 2 | 2013-12-03 |
Handling Of Write Operations Within A Memory Device
App 20130258760 - HOLD; Betina | 2013-10-03 |
Using A Precharge Characteristics Of A Node To Validate A Previous Data/signal Value Represented By A Discharge Of Said Node
App 20130155797 - HOLD; Betina | 2013-06-20 |
Memory Device And A Method Of Operating Such A Memory Device In A Speculative Read Mode
App 20130148443 - HOLD; Betina | 2013-06-13 |
Memory device and method of performing a read operation within a memory device
App 20130077416 - Hold; Betina | 2013-03-28 |
Techniques For Providing A Direct Injection Semiconductor Memory Device
App 20130077425 - VAN BUSKIRK; Michael A. ; et al. | 2013-03-28 |
Techniques for providing a source line plane
Grant 8,319,294 - Hold November 27, 2 | 2012-11-27 |
Techniques for providing a direct injection semiconductor memory device
Grant 8,315,099 - Van Buskirk , et al. November 20, 2 | 2012-11-20 |
Techniques For Reading From And/or Writing To A Semiconductor Memory Device
App 20110216608 - Hold; Betina ; et al. | 2011-09-08 |
Techniques For Providing A Direct Injection Semiconductor Memory Device
App 20110019482 - Van Buskirk; Michael A. ; et al. | 2011-01-27 |
Controlling signal levels on a signal line within an integrated circuit
Grant 7,830,176 - Hold , et al. November 9, 2 | 2010-11-09 |
Techniques For Providing A Source Line Plane
App 20100210075 - HOLD; Betina | 2010-08-19 |
Controlling power supply to memory cells
Grant 7,688,668 - Hold March 30, 2 | 2010-03-30 |
Controlling power supply to memory cells
App 20090135661 - Hold; Betina | 2009-05-28 |
Timing control for sense amplifiers in a memory circuit
Grant 7,339,842 - Hold March 4, 2 | 2008-03-04 |
Timing Control For Sense Amplifiers In A Memory Circuit
App 20080043555 - Hold; Betina | 2008-02-21 |
Controlling signal levels on a signal line within an integrated circuit
App 20080029839 - Hold; Betina ; et al. | 2008-02-07 |
Dual port memory core cell architecture with matched bit line capacitances
Grant 7,002,258 - Mali , et al. February 21, 2 | 2006-02-21 |
Dual port memory core cell architecture with matched bit line capacitances
App 20050121810 - Mali, Jim ; et al. | 2005-06-09 |
Load independent single ended sense amplifier
Grant 6,597,613 - Becker , et al. July 22, 2 | 2003-07-22 |
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