Holbrook; Allison

Patent Applications and Registrations

Patent applications and USPTO patent grants for Holbrook; Allison.The latest application filed is for "self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications".

Company Profile

0.15.5

Holbrook; Allison - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications Grant 7,943,980 - Fang , et al. May 17, 2	2011-05-17
Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications Grant 7,906,395 - Fang , et al. March 15, 2	2011-03-15
Self-aligned Patterning Method By Using Non-conformal Film And Etch Back For Flash Memory And Other Semiconductur Applications App 20110012191 - FANG; Shenqing ; et al.	2011-01-20
Self-aligned Patterning Method By Using Non-conformal Film And Etch Back For Flash Memory And Other Semiconductur Applications App 20110013449 - FANG; Shenqing ; et al.	2011-01-20
Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications Grant 7,803,680 - Fang , et al. September 28, 2	2010-09-28
Integrated circuit memory system employing silicon rich layers Grant 7,675,104 - Joshi , et al. March 9, 2	2010-03-09
Enhanced etching of a high dielectric constant layer Grant 7,498,222 - Foster , et al. March 3, 2	2009-03-03
Isolation region bird's beak suppression Grant 7,465,644 - Chan , et al. December 16, 2	2008-12-16
Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications App 20080171416 - Fang; Shenging ; et al.	2008-07-17
Method For Manufacturing A Memory Device App 20080096357 - Suh; Youseok ; et al.	2008-04-24
Integrated Circuit Memory System Employing Silicon Rich Layers App 20080023751 - Joshi; Amol Ramesh ; et al.	2008-01-31
Method for making an ultra thin FDSOI device with improved short-channel performance Grant 6,975,014 - Krivokapic , et al. December 13, 2	2005-12-13
Method for lateral trimming of spacers Grant 6,821,713 - Holbrook , et al. November 23, 2	2004-11-23
Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate Grant 6,709,924 - Yu , et al. March 23, 2	2004-03-23
Fully depleted SOI device with tungsten damascene contacts and method of forming same Grant 6,605,843 - Krivokapic , et al. August 12, 2	2003-08-12
Reliable particle removal following a process chamber wet clean Grant 6,472,326 - Holbrook , et al. October 29, 2	2002-10-29
Method for fabricating T-shaped transistor gate Grant 6,448,163 - Holbrook , et al. September 10, 2	2002-09-10
Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process Grant 6,358,362 - En , et al. March 19, 2	2002-03-19
Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process Grant 6,060,328 - En , et al. May 9, 2	2000-05-09
In-situ etch of BARC layer during formation of local interconnects Grant 5,920,796 - Wang , et al. July 6, 1	1999-07-06

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