Hoekstra; George P.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Hoekstra; George P..The latest application filed is for "memory reliability using error-correcting code".
Company Profile
0.40.34
- Hoekstra; George P. - Austin TX
- Hoekstra; George P. - Fair Oaks CA
Patent Activity
| Patent | Date |
|---|---|
| Memory reliability using error-correcting code Grant 9,772,901 - Hoekstra , et al. September 26, 2 | 2017-09-26 |
| Memory with redundancy Grant 9,672,938 - Hoekstra , et al. June 6, 2 | 2017-06-06 |
| Memory Reliability Using Error-correcting Code App 20160328286 - HOEKSTRA; GEORGE P. ; et al. | 2016-11-10 |
| Error repair location cache Grant 9,477,548 - Hoekstra , et al. October 25, 2 | 2016-10-25 |
| Adaptive error correction codes (ECCs) for electronic memories Grant 9,425,829 - Ramaraju , et al. August 23, 2 | 2016-08-23 |
| Error correction with secondary memory Grant 9,396,064 - Hoekstra , et al. July 19, 2 | 2016-07-19 |
| Memory redundancy to replace addresses with multiple errors Grant 9,389,954 - Pelley , et al. July 12, 2 | 2016-07-12 |
| Error correction with extended CAM Grant 9,323,602 - Hoekstra , et al. April 26, 2 | 2016-04-26 |
| Memory column drowsy control Grant 9,317,087 - Ramaraju , et al. April 19, 2 | 2016-04-19 |
| ADAPTIVE ERROR CORRECTION CODES (ECCs) FOR ELECTRONIC MEMORIES App 20160080002 - Ramaraju; Ravindraraj ; et al. | 2016-03-17 |
| Command Set Extension for Non-Volatile Memory App 20160062656 - Ramaraju; Ravindraraj ; et al. | 2016-03-03 |
| Error Repair Location Cache App 20160034344 - Hoekstra; George P. ; et al. | 2016-02-04 |
| Temperature threshold circuit with hysteresis Grant 9,225,337 - Pelley , et al. December 29, 2 | 2015-12-29 |
| Memory with word line access control Grant 9,224,439 - Ramaraju , et al. December 29, 2 | 2015-12-29 |
| Memory ECC with hard and soft error detection and management Grant 9,208,024 - Pelley , et al. December 8, 2 | 2015-12-08 |
| Error Correction With Secondary Memory App 20150318871 - HOEKSTRA; GEORGE P. ; et al. | 2015-11-05 |
| Memory With Redundancy App 20150302939 - HOEKSTRA; GEORGE P. ; et al. | 2015-10-22 |
| Temperature Threshold Circuit With Hysteresis App 20150244375 - Pelley; Perry H. ; et al. | 2015-08-27 |
| Memory Redundancy to Replace Addresses with Multiple Errors App 20150242269 - Pelley; Perry H. ; et al. | 2015-08-27 |
| Memory with power savings for unnecessary reads Grant 9,117,498 - Ramaraju , et al. August 25, 2 | 2015-08-25 |
| Memory ECC with Hard and Soft Error Detection and Management App 20150199233 - Pelley; Perry H. ; et al. | 2015-07-16 |
| Memory With Power Savings For Unnecessary Reads App 20140269131 - Ramaraju; Ravindraraj ; et al. | 2014-09-18 |
| Error Correction With Extended Cam App 20140201597 - Hoekstra; George P. ; et al. | 2014-07-17 |
| Memory With Word Line Access Control App 20140003172 - RAMARAJU; RAVINDRARAJ ; et al. | 2014-01-02 |
| Memory Column Drowsy Control App 20130290753 - Ramaraju; Ravindraraj ; et al. | 2013-10-31 |
| Dynamic logic circuit Grant 8,487,656 - Ramaraju , et al. July 16, 2 | 2013-07-16 |
| Dynamic logic circuit Grant 8,487,657 - Hoekstra , et al. July 16, 2 | 2013-07-16 |
| Memory system with error correction and method of operation Grant 8,402,327 - Pelley, III , et al. March 19, 2 | 2013-03-19 |
| Dynamic random access memory (DRAM) refresh Grant 8,400,859 - Pelley, III , et al. March 19, 2 | 2013-03-19 |
| Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory Grant 8,090,913 - Pelley, III , et al. January 3, 2 | 2012-01-03 |
| Dynamic Random Access Memory (dram) Refresh App 20110255357 - PELLEY, III; PERRY H. ; et al. | 2011-10-20 |
| Dynamic random access memory (DRAM) refresh Grant 7,990,795 - Pelley, III , et al. August 2, 2 | 2011-08-02 |
| Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions Grant 7,941,637 - Pelley, III , et al. May 10, 2 | 2011-05-10 |
| Multi-core Processing System App 20110093660 - PELLEY, III; PERRY H. ; et al. | 2011-04-21 |
| Dynamic Random Access Memory (dram) Refresh App 20100208537 - Pelley, III; Perry H. ; et al. | 2010-08-19 |
| Memory System With Error Correction And Method Of Operation App 20100107037 - Pelley, III; Perry H. ; et al. | 2010-04-29 |
| Multi-core Processing System App 20090259825 - Pelley, III; Perry H. ; et al. | 2009-10-15 |
| Double-rate memory Grant 7,564,738 - Pelley, III , et al. July 21, 2 | 2009-07-21 |
| Level shifting circuit Grant 7,443,223 - Bajkowski , et al. October 28, 2 | 2008-10-28 |
| Circuit and method for latch bypass Grant 7,362,134 - Bajkowski , et al. April 22, 2 | 2008-04-22 |
| Memory device with a data hold latch Grant 7,349,266 - Ramaraju , et al. March 25, 2 | 2008-03-25 |
| Level Shifting Circuit App 20080054980 - Bajkowski; Maciej ; et al. | 2008-03-06 |
| Circuit and method for latch bypass App 20070222480 - Bajkowski; Maciej ; et al. | 2007-09-27 |
| System and method for memory array access with fast address decoder App 20070094479 - Bearden; David R. ; et al. | 2007-04-26 |
| Data processing system having translation lookaside buffer valid bits with lock and method therefor Grant 7,185,170 - Ramaraju , et al. February 27, 2 | 2007-02-27 |
| Dynamic latch having integral logic function and method therefor Grant 7,164,293 - Ramaraju , et al. January 16, 2 | 2007-01-16 |
| Data processing system having translation lookaside buffer valid bits with lock and method therefor App 20060047935 - Ramaraju; Ravindraraj ; et al. | 2006-03-02 |
| Dynamic latch having integral logic function and method therefor App 20060022714 - Ramaraju; Ravindraraj ; et al. | 2006-02-02 |
| Memory device with a data hold latch App 20050286327 - Ramaraju, Ravindraraj ; et al. | 2005-12-29 |
| Domino comparator capable for use in a memory array Grant 6,928,005 - Ramaraju , et al. August 9, 2 | 2005-08-09 |
| Multistage dynamic domino circuit with internally generated delay reset clock App 20050110522 - Hoekstra, George P. | 2005-05-26 |
| Domino comparator capable for use in a memory array App 20050105324 - Ramaraju, Ravindraraj ; et al. | 2005-05-19 |
| Hysteresis reduced sense amplifier and method of operation Grant 6,608,789 - Sullivan , et al. August 19, 2 | 2003-08-19 |
| Hysteresis reduced sense amplifier and method of operation App 20030117873 - Sullivan, Steven C. ; et al. | 2003-06-26 |
| Bit line precharge in a bimos ram Grant 4,899,317 - Hoekstra , et al. February 6, 1 | 1990-02-06 |
| Testing arrangement for a DRAM with redundancy Grant 4,866,676 - Crisp , et al. September 12, 1 | 1989-09-12 |
| RAM with dual precharge circuit and write recovery circuitry Grant 4,802,129 - Hoekstra , et al. January 31, 1 | 1989-01-31 |
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