Ho; Yueh-Se

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ho; Yueh-Se.The latest application filed is for "semiconductor package having enlarged gate pad and method of making the same".

Company Profile

7.142.126

Ho; Yueh-Se - Sunnyvale CA
Ho; Yueh-Se - Raleigh NC

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor package having enlarged gate pad and method of making the same Grant 11,222,858 - Xue , et al. January 11, 2	2022-01-11
Semiconductor Package Having Enlarged Gate Pad And Method Of Making The Same App 20210398926 - Xue; Yan Xun ; et al.	2021-12-23
Method of making reverse conducting insulated gate bipolar transistor Grant 11,101,137 - Niu , et al. August 24, 2	2021-08-24
Semiconductor package and method of making the same Grant 11,069,604 - Zhang , et al. July 20, 2	2021-07-20
Power Module Having Interconnected Base Plate With Molded Metal And Method Of Making The Same App 20210175155 - Niu; Zhiqiang ; et al.	2021-06-10
Semiconductor package having high mechanical strength Grant 10,991,660 - Wang , et al. April 27, 2	2021-04-27
Common source land grid array package Grant 10,991,680 - Xue , et al. April 27, 2	2021-04-27
Common Source Land Grid Array Package App 20210083088 - Xue; Yan Xun ; et al.	2021-03-18
Semiconductor Package And Method Of Making The Same App 20200194395 - Zhang; Xiaotian ; et al.	2020-06-18
Semiconductor Package And Method Of Making The Same App 20200194347 - Xue; Yan Xun ; et al.	2020-06-18
Vertical gallium nitride Schottky diode Grant 10,573,762 - Zhu , et al. Feb	2020-02-25
Methods for fabricating anode shorted field stop insulated gate bipolar transistor Grant 10,522,666 - Bhalla , et al. Dec	2019-12-31
Vertical Gallium Nitride Schottky Diode App 20190296157 - Zhu; TingGang ; et al.	2019-09-26
Termination structure for gallium nitride Schottky diode including junction barriar diodes Grant 10,333,006 - Zhu , et al.	2019-06-25
Semiconductor Package Having High Mechanical Strength App 20190189569 - Wang; Long-Ching ; et al.	2019-06-20
Termination Structure For Gallium Nitride Schottky Diode Including Junction Barriar Diodes App 20180323315 - Zhu; TingGang ; et al.	2018-11-08
Methods for fabricating anode shorted field stop insulated gate bipolar transistor Grant 10,050,134 - Bhalla , et al. August 14, 2	2018-08-14
Termination structure for gallium nitride Schottky diode Grant 10,038,106 - Zhu , et al. July 31, 2	2018-07-31
Methods For Fabricating Anode Shorted Field Stop Insulated Gate Bipolar Transistor App 20180204937 - Bhalla; Anup ; et al.	2018-07-19
Semiconductor package of a flipped MOSFET chip and a multi-based die paddle with top surface groove-divided multiple connecting areas for connection to the flipped MOSFET electrodes Grant 9,929,076 - Xue , et al. March 27, 2	2018-03-27
Power device and preparation method thereof Grant 9,837,386 - Zhang , et al. December 5, 2	2017-12-05
Termination Structure For Gallium Nitride Schottky Diode App 20170301800 - Zhu; TingGang ; et al.	2017-10-19
Power semiconductor package device having locking mechanism, and preparation method thereof Grant 9,786,583 - Xue , et al. October 10, 2	2017-10-10
Battery protection package and process of making the same Grant 9,768,146 - Niu , et al. September 19, 2	2017-09-19
Combined packaged power semiconductor device Grant 9,735,094 - Ho , et al. August 15, 2	2017-08-15
Termination structure for gallium nitride schottky diode Grant 9,728,655 - Zhu , et al. August 8, 2	2017-08-08
Power Device And Preparation Method Thereof App 20170200705 - Zhang; Xiaotian ; et al.	2017-07-13
Embedded package and method thereof Grant 9,685,430 - Niu , et al. June 20, 2	2017-06-20
Semiconductor package with small gate clip and assembly method Grant 9,679,833 - Xue , et al. June 13, 2	2017-06-13
Battery Protection Package And Process Of Making The Same App 20170098626 - Niu; Zhiqiang ; et al.	2017-04-06
Battery protection package and process of making the same Grant 9,564,406 - Niu , et al. February 7, 2	2017-02-07
Battery Protection Package And Process Of Making The Same App 20170033060 - Niu; Zhiqiang ; et al.	2017-02-02
Semiconductor Package With Small Gate Clip And Assembly Method App 20160379918 - Xue; Yan Xun ; et al.	2016-12-29
Power Semiconductor Package Device Having Locking Mechanism, And Preparation Method Thereof App 20160379917 - Xue; Yan Xun ; et al.	2016-12-29
Termination structure for gallium nitride schottky diode App 20160372610 - Zhu; TingGang ; et al.	2016-12-22
Wafer process for molded chip scale package (MCSP) with thick backside metallization Grant 9,520,380 - Xue , et al. December 13, 2	2016-12-13
Methods for fabricating anode shorted field stop insulated gate bipolar transistor Grant 9,478,646 - Bhalla , et al. October 25, 2	2016-10-25
Combined Packaged Power Semiconductor Device App 20160307830 - Ho; Yueh-Se ; et al.	2016-10-20
Semiconductor package with small gate clip and assembly method Grant 9,472,491 - Xue , et al. October 18, 2	2016-10-18
Methods For Fabricating Anode Shorted Field Stop Insulated Gate Bipolar Transistor App 20160284797 - Bhalla; Anup ; et al.	2016-09-29
Combined packaged power semiconductor device Grant 9,437,530 - Ho , et al. September 6, 2	2016-09-06
Top exposed semiconductor chip package Grant 9,412,684 - Xue , et al. August 9, 2	2016-08-09
Protection circuit including vertical gallium nitride schottky diode and PN junction diode Grant 9,406,661 - Zhu , et al. August 2, 2	2016-08-02
Power semiconductor package device having locking mechanism, and preparation method thereof Grant 9,397,029 - Xue , et al. July 19, 2	2016-07-19
Method for packaging a power device with bottom source electrode Grant 9,391,005 - Xue , et al. July 12, 2	2016-07-12
Method For Packaging A Power Device With Bottom Source Electrode App 20160155688 - Xue; Yan Xun ; et al.	2016-06-02
Methods and configuration for manufacturing flip chip contact (FCC) power package Grant 9,337,132 - Sun , et al. May 10, 2	2016-05-10
A Semiconductor Package Of A Flipped Mosfet App 20160104661 - Xue; Yan Xun ; et al.	2016-04-14
Embedded Package And Method Thereof App 20160099238 - Niu; Zhiqiang ; et al.	2016-04-07
Power semiconductor device and preparation method thereof Grant 9,305,870 - Xue , et al. April 5, 2	2016-04-05
Semiconductor Package With Small Gate Clip And Assembly Method App 20160093559 - Xue; Yan Xun ; et al.	2016-03-31
Wafer Process For Molded Chip Scale Package (mcsp) With Thick Backside Metallization App 20160079203 - Xue; Yan Xun ; et al.	2016-03-17
Packaging structure of a semiconductor device Grant 9,281,265 - Ho , et al. March 8, 2	2016-03-08
Power Semiconductor Device And Preparation Method Thereof App 20160056096 - Xue; Yan Xun ; et al.	2016-02-25
Semiconductor Device Employing Aluminum Alloy Lead-frame With Anodized Aluminum App 20160056098 - Xue; Yan Xun ; et al.	2016-02-25
Embedded package and method thereof Grant 9,269,699 - Niu , et al. February 23, 2	2016-02-23
Wafer process for molded chip scale package (MCSP) with thick backside metallization Grant 9,245,861 - Xue , et al. January 26, 2	2016-01-26
Combined packaged power semiconductor device Grant 9,214,417 - Ho , et al. December 15, 2	2015-12-15
Power semiconductor device and preparation method thereof Grant 9,214,419 - Xue , et al. December 15, 2	2015-12-15
Combined Packaged Power Semiconductor Device App 20150357267 - Ho; Yueh-Se ; et al.	2015-12-10
Substrateless Power Device Packages App 20150340301 - Feng; Tao ; et al.	2015-11-26
Method for preparing semiconductor devices applied in flip chip technology Grant 9,196,534 - Xue , et al. November 24, 2	2015-11-24
Embedded Package And Method Thereof App 20150325559 - Niu; Zhiqiang ; et al.	2015-11-12
Stacked dual-chip packaging structure and preparation method thereof Grant 9,184,117 - Ho , et al. November 10, 2	2015-11-10
Semiconductor package with small gate clip and assembly method Grant 9,171,788 - Xue , et al. October 27, 2	2015-10-27
Stacked dual chip package having leveling projections Grant 9,165,866 - Yilmaz , et al. October 20, 2	2015-10-20
Semiconductor Device Employing Aluminum Alloy Lead-frame With Anodized Aluminum App 20150262925 - Xue; Yan Xun ; et al.	2015-09-17
Substrateless power device packages Grant 9,136,154 - Feng , et al. September 15, 2	2015-09-15
Bottom source substrateless power MOSFET Grant 9,136,379 - Ho , et al. September 15, 2	2015-09-15
Power Semiconductor Device And Preparation Method Thereof App 20150249045 - Xue; Yan Xun ; et al.	2015-09-03
Combined Packaged Power Semiconductor Device App 20150243589 - Ho; Yueh-Se ; et al.	2015-08-27
Protection Circuit Including Vertical Gallium Nitride Schottky Diode And Schottky Diode App 20150228729 - Zhu; TingGang ; et al.	2015-08-13
Semiconductor including cup-shaped leadframe packaging techniques Grant 9,040,356 - Chang , et al. May 26, 2	2015-05-26
Flip Chip Contact (fcc) Power Package App 20150102425 - Sun; Ming ; et al.	2015-04-16
Vertical gallium nitride Schottky diode Grant 8,994,140 - Zhu , et al. March 31, 2	2015-03-31
Method For Packaging A Power Device With Bottom Source Electrode App 20150087114 - Xue; Yan Xun ; et al.	2015-03-26
Substrateless power device packages Grant 8,987,878 - Feng , et al. March 24, 2	2015-03-24
Wafer level chip scale package and process of manufacture Grant 8,981,464 - Feng , et al. March 17, 2	2015-03-17
Substrateless Power Device Packages App 20150056752 - Feng; Tao ; et al.	2015-02-26
Stacked multi-chip bottom source semiconductor device and preparation method thereof Grant 8,952,509 - Yilmaz , et al. February 10, 2	2015-02-10
Packaging Structure Of A Semiconductor Device App 20150021753 - Ho; Yueh-Se ; et al.	2015-01-22
Stacked power semiconductor device using dual lead frame Grant 8,933,518 - Xue , et al. January 13, 2	2015-01-13
A Semiconductor Package Of A Flipped Mosfet App 20140361418 - Xue; Yan Xun ; et al.	2014-12-11
Wafer level chip scale package Grant 8,890,296 - Ho , et al. November 18, 2	2014-11-18
Bottom Source Substrateless Power Mosfet App 20140319601 - Ho; Yueh-Se ; et al.	2014-10-30
Wafer Process For Molded Chip Scale Package (mcsp) With Thick Backside Metallization App 20140315350 - Xue; Yan Xun ; et al.	2014-10-23
Semiconductor package and fabrication method thereof Grant 8,865,523 - Ho , et al. October 21, 2	2014-10-21
Semiconductor Package And Fabrication Method Thereof App 20140264805 - Ho; Yueh-Se ; et al.	2014-09-18
Vertical Gallium Nitride Schottky Diode App 20140252372 - Zhu; TingGang ; et al.	2014-09-11
Wafer Level Chip Scale Package And Process Of Manufacture App 20140239383 - Feng; Tao ; et al.	2014-08-28
Method For Preparing Semiconductor Devices Applied In Flip Chip Technology App 20140242756 - Xue; Yan Xun ; et al.	2014-08-28
Multi-layer lead frame package and method of fabrication Grant 8,815,649 - Lu , et al. August 26, 2	2014-08-26
Virtually substrate-less composite power semiconductor device Grant 8,796,858 - Feng , et al. August 5, 2	2014-08-05
Packaging method with backside wafer dicing Grant 8,785,296 - Xue , et al. July 22, 2	2014-07-22
Packaging method of molded wafer level chip scale package (WLCSP) Grant 8,778,735 - Xue , et al. July 15, 2	2014-07-15
Stacked Power Semiconductor Device Using Dual Lead Frame App 20140191334 - Xue; Yan Xun ; et al.	2014-07-10
Vertical gallium nitride Schottky diode Grant 8,772,144 - Zhu , et al. July 8, 2	2014-07-08
Copper Wire Bonding Structure In Semiconductor Device And Fabrication Method Thereof App 20140175628 - Pan; Hua ; et al.	2014-06-26
Wafer level chip scale package and process of manufacture Grant 8,716,063 - Feng , et al. May 6, 2	2014-05-06
Semiconductor device employing aluminum alloy lead-frame with anodized aluminum Grant 8,716,069 - Xue , et al. May 6, 2	2014-05-06
Stacked Dual-chip Packaging Structure And Preparation Method Thereof App 20140117523 - Ho; Yueh-Se ; et al.	2014-05-01
Semiconductor Device Employing Aluminum Alloy Lead-frame With Anodized Aluminum App 20140091446 - Xue; Yan Xun ; et al.	2014-04-03
Combined packaged power semiconductor device Grant 8,686,546 - Ho , et al. April 1, 2	2014-04-01
Top Exposed Semiconductor Chip Package App 20140035116 - Xue; Yan Xun ; et al.	2014-02-06
Wafer level package structure and the fabrication method thereof Grant 8,642,385 - Xue , et al. February 4, 2	2014-02-04
Top exposed package and assembly method Grant 8,586,414 - Xue , et al. November 19, 2	2013-11-19
Multi-layer Lead Frame Package And Method Of Fabrication App 20130302946 - Lu; Jun ; et al.	2013-11-14
Stacked dual chip package and method of fabrication Grant 8,581,376 - Yilmaz , et al. November 12, 2	2013-11-12
Bottom source power MOSFET with substrateless and manufacturing method thereof Grant 8,569,169 - Ho , et al. October 29, 2	2013-10-29
Power device with bottom source electrode Grant 8,564,110 - Xue , et al. October 22, 2	2013-10-22
Flip chip contact (FCC) power package Grant 8,564,049 - Sun , et al. October 22, 2	2013-10-22
Packaging method of molded wafer level chip scale package (WLCSP) Grant 8,563,361 - Xue , et al. October 22, 2	2013-10-22
Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process Grant 8,563,417 - Lu , et al. October 22, 2	2013-10-22
Multi-layer lead frame package and method of fabrication Grant 8,513,784 - Lu , et al. August 20, 2	2013-08-20
Packaging Method Of Molded Wafer Level Chip Scale Package (wlcsp) App 20130210195 - Xue; Yan Xun ; et al.	2013-08-15
Packaging Method With Backside Wafer Dicing App 20130210215 - Xue; Yan Xun ; et al.	2013-08-15
Semiconductor package of a flipped MOSFET and its manufacturing method Grant 8,481,368 - Xue , et al. July 9, 2	2013-07-09
Package structure for DC-DC converter Grant 8,476,752 - Ho , et al. July 2, 2	2013-07-02
Wafer Level Chip Scale Package App 20130134502 - Ho; Yueh-Se ; et al.	2013-05-30
Method For Packaging Ultra-thin Chip With Solder Ball Thermo-compression In Wafer Level Packaging Process App 20130130443 - Lu; Jun ; et al.	2013-05-23
Vertical Gallium Nitride Schottky Diode App 20130119393 - Zhu; TingGang ; et al.	2013-05-16
Stacked power semiconductor device using dual lead frame and manufacturing method Grant 8,436,429 - Xue , et al. May 7, 2	2013-05-07
Wafer level chip scale packaging Grant 8,426,960 - Sun , et al. April 23, 2	2013-04-23
Wafer Level Package Structure And The Fabrication Method Thereof App 20130037935 - Xue; Yan Xun ; et al.	2013-02-14
Methods For Fabricating Anode Shorted Field Stop Insulated Gate Bipolar Transistor App 20130029461 - BHALLA; ANUP ; et al.	2013-01-31
Wafer level chip scale package Grant 8,362,606 - Ho , et al. January 29, 2	2013-01-29
Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers Grant 8,330,264 - Sun , et al. December 11, 2	2012-12-11
Stacked Power Semiconductor Device Using Dual Lead Frame And Manufacturing Method App 20120299119 - Xue; Yan Xun ; et al.	2012-11-29
Package Structure For Dc-dc Converter App 20120248593 - Ho; Yueh-Se ; et al.	2012-10-04
Power Device With Bottom Source Electrode And Preparation Method App 20120235289 - Xue; Yan Xun ; et al.	2012-09-20
Virtually Substrate-less Composite Power Semiconductor Device App 20120235306 - Feng; Tao ; et al.	2012-09-20
Packaging Configurations For Vertical Electronic Devices Using Conductive Traces Disposed On Laminated Board Layers App 20120205803 - Sun; Ming ; et al.	2012-08-16
Virtually substrate-less composite power semiconductor device and method Grant 8,242,013 - Feng , et al. August 14, 2	2012-08-14
Package structure for DC-DC converter Grant 8,217,503 - Ho , et al. July 10, 2	2012-07-10
Top exposed Package and Assembly Method App 20120146202 - Xue; Yan Xun ; et al.	2012-06-14
Substrateless Power Device Packages App 20120104580 - Feng; Tao ; et al.	2012-05-03
Integrated circuit package for semiconductior devices with improved electric resistance and inductance Grant 8,169,062 - Luo , et al. May 1, 2	2012-05-01
Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers Grant 8,168,477 - Sun , et al. May 1, 2	2012-05-01
Package Structure for DC-DC Converter App 20120061813 - Ho; Yueh-Se ; et al.	2012-03-15
Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates Grant 8,124,453 - Sun , et al. February 28, 2	2012-02-28
Bottom Source Power Mosfet With Substrateless And Manufacturing Method Thereof App 20120032259 - Ho; Yueh-Se ; et al.	2012-02-09
Wafer Level Chip Scale Package App 20120025298 - Ho; Yueh-Se ; et al.	2012-02-02
Combined Packaged Power Semiconductor Device App 20110309454 - Ho; Yueh-Se ; et al.	2011-12-22
Integrated circuit package for semiconductor devices with improved electric resistance and inductance Grant 8,067,822 - Luo , et al. November 29, 2	2011-11-29
Standing chip scale package Grant 8,058,727 - Feng , et al. November 15, 2	2011-11-15
Standing chip scale package Grant 8,053,891 - Feng , et al. November 8, 2	2011-11-08
Virtually Substrate-less Composite Power Semiconductor Device and Method App 20110241214 - Feng; Tao ; et al.	2011-10-06
Multi-layer Lead Frame Package And Method Of Fabrication App 20110227205 - Lu; Jun ; et al.	2011-09-22
Stacked Dual Chip Package And Method Of Fabrication App 20110227207 - Yilmaz; Hamza ; et al.	2011-09-22
Integrated circuit package for semiconductior devices with improved electric resistance and inductance App 20110221005 - Luo; Leeshawn ; et al.	2011-09-15
Semiconductor Package Of A Flipped Mosfet And Its Manufacturing Method App 20110193208 - Xue; Yan Xun ; et al.	2011-08-11
Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates App 20110143499 - Sun; Ming ; et al.	2011-06-16
Wafer level chip scale package and process of manufacture Grant 7,955,893 - Feng , et al. June 7, 2	2011-06-07
Wafer Level Chip Scale Package And Process Of Manufacture App 20110108896 - FENG; TAO ; et al.	2011-05-12
Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers App 20110076808 - Sun; Ming ; et al.	2011-03-31
Standing Chip Scale Package App 20100320531 - Feng; Tao ; et al.	2010-12-23
Packages for electronic devices implemented with laminated board with a top and a bottom patterned metal layers Grant 7,838,977 - Sun , et al. November 23, 2	2010-11-23
Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backside Grant 7,829,989 - Sun , et al. November 9, 2	2010-11-09
Method of fabricating a semiconductor device employing electroless plating Grant 7,811,904 - Feng , et al. October 12, 2	2010-10-12
Standing chip scale package App 20090321929 - Feng; Tao ; et al.	2009-12-31
Inverted J-lead for power devices Grant 7,633,140 - Luo , et al. December 15, 2	2009-12-15
Chip Scale Surface Mount Package For Semiconductor Device And Process Of Fabricating The Same App 20090278179 - Zandman; Felix ; et al.	2009-11-12
Semiconductor Packaging Techniques App 20090256246 - Chang; Mike ; et al.	2009-10-15
Semiconductor die package including cup-shaped leadframe Grant 7,595,547 - Chang , et al. September 29, 2	2009-09-29
Chip scale surface mount package for semiconductor device and process of fabricating the same Grant 7,589,396 - Zandman , et al. September 15, 2	2009-09-15
Wafer Level Chip Scale Package And Process Of Manufacture App 20090194880 - Feng; Tao ; et al.	2009-08-06
Wafer Level Chip Scale Packaging App 20090160045 - Sun; Ming ; et al.	2009-06-25
Integrated circuit package for semiconductior devices with improved electric resistance and inductance App 20090014853 - Luo; Leeshawn ; et al.	2009-01-15
Method of forming ultra thin chips of power devices App 20080242052 - Feng; Tao ; et al.	2008-10-02
Flip chip contact (FCC) power package App 20080211070 - Sun; Ming ; et al.	2008-09-04
Method of fabricating a semiconductor device employing electroless plating App 20080182387 - Feng; Tao ; et al.	2008-07-31
Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area Grant 7,391,100 - Luo , et al. June 24, 2	2008-06-24
Chip scale surface mount package for semiconductor device and process of fabricating the same App 20070235774 - Zandman; Felix ; et al.	2007-10-11
Common drain dual semiconductor chip scale package and method of fabricating same App 20070148875 - Sun; Ming ; et al.	2007-06-28
Chip scale surface mount package for semiconductor device and process of fabricating the same Grant 7,211,877 - Zandman , et al. May 1, 2	2007-05-01
Power semiconductor package Grant 7,208,818 - Luo , et al. April 24, 2	2007-04-24
Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates App 20070085187 - Sun; Ming ; et al.	2007-04-19
Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers App 20070080443 - Sun; Ming ; et al.	2007-04-12
Wafer-level method for metallizing source, gate and drain contact areas of semiconductor die App 20070075406 - Ho; Yueh-Se ; et al.	2007-04-05
Semiconductor package having plate interconnections App 20070057368 - Ho; Yueh-Se ; et al.	2007-03-15
High speed switching MOSFETS using multi-parallel die packages with/without special leadframes Grant 7,183,616 - Bhalla , et al. February 27, 2	2007-02-27
Flip chip contact (FCC) power package App 20060145319 - Sun; Ming ; et al.	2006-07-06
Power semiconductor package App 20060017141 - Luo; Leeshawn ; et al.	2006-01-26
Multiple device package App 20050280133 - Luo, Leeshawn ; et al.	2005-12-22
Integrated circuit package for semiconductor devices with improved electric resistance and inductance App 20050145996 - Luo, Leeshawn ; et al.	2005-07-07
Semiconductor assembly with package using cup-shaped lead-frame Grant 6,909,170 - Chang , et al. June 21, 2	2005-06-21
Inverted J-lead package for power devices App 20050127532 - Luo, Leeshawn ; et al.	2005-06-16
Chip scale surface mount package for semiconductor device and process of fabricating the same Grant 6,876,061 - Zandman , et al. April 5, 2	2005-04-05
Integrated circuit package for semiconductor devices with improved electric resistance and inductance Grant 6,841,852 - Luo , et al. January 11, 2	2005-01-11
Semiconductor die package including cup-shaped leadframe Grant 6,744,124 - Chang , et al. June 1, 2	2004-06-01
Integrated circuit package for semicoductor devices with improved electric resistance and inductance App 20040004272 - Luo, Leeshawn ; et al.	2004-01-08
High speed switching mosfets using multi-parallel die packages with/without special leadframes App 20030183924 - Bhalla, Anup ; et al.	2003-10-02
Chip scale surface mount package for semiconductor device and process of fabricating the same Grant 6,562,647 - Zandman , et al. May 13, 2	2003-05-13
Semiconductor assembly with package using cup-shaped lead frame App 20030057532 - Chang, Mike ; et al.	2003-03-27
Chip scale surface mount package for semiconductor device and process of fabricating the same App 20020185710 - Zandman, Felix ; et al.	2002-12-12
Chip scale surface mount package for semiconductor device and process of fabricating the same Grant 6,441,475 - Zandman , et al. August 27, 2	2002-08-27
Vertical structure for semiconductor wafer-level chip scale packages Grant 6,392,290 - Kasem , et al. May 21, 2	2002-05-21
Chip scale surface mount packages for semiconductor device and process of fabricating the same Grant 6,316,287 - Zandman , et al. November 13, 2	2001-11-13
Chip scale surface mount package for semiconductor device and process of fabricating the same App 20010016369 - Zandman, Felix ; et al.	2001-08-23
Process of fabricating a chip scale surface mount package for semiconductor device Grant 6,271,060 - Zandman , et al. August 7, 2	2001-08-07
Chip scale surface mount packages for semiconductor device App 20010009298 - Zandman, Felix ; et al.	2001-07-26
Chip scale surface mount package for semiconductor device and process of fabricating the same App 20010000631 - Zandman, Felix ; et al.	2001-05-03
Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation Grant 5,767,578 - Chang , et al. June 16, 1	1998-06-16
Surface mount and flip chip technology for total integrated circuit isolation Grant 5,757,081 - Chang , et al. May 26, 1	1998-05-26
Surface mount and flip chip technology for total integrated circuit isolation Grant 5,753,529 - Chang , et al. May 19, 1	1998-05-19
Trenched DMOS transistor fabrication having thick termination region oxide Grant 5,639,676 - Hshieh , et al. June 17, 1	1997-06-17
Trenched DMOS transistor having thick field oxide in termination region Grant 5,578,851 - Hshieh , et al. November 26, 1	1996-11-26
Trenched DMOS transistor with channel block at cell trench corners Grant 5,468,982 - Hshieh , et al. November 21, 1	1995-11-21
Trenched DMOS transistor fabrication using six masks Grant 5,316,959 - Kwan , et al. May 31, 1	1994-05-31
Shared current loop, multiple field apparatus and process for plasma processing Grant 4,738,761 - Bobbio , et al. April 19, 1	1988-04-19

Company Registrations

SEC

0001522313

Ho Yueh-Se