Ho; William Wai Yan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ho; William Wai Yan.The latest application filed is for "using a barycenter compact model for a circuit network".

Company Profile

0.41.1

Ho; William Wai Yan - San Jose CA
Ho; William Wai Yan - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Using a Barycenter compact model for a circuit network Grant 10,885,255 - Ho January 5, 2	2021-01-05
Partitioning a system graph for circuit simulation to obtain an exact solution Grant 10,558,772 - Ho Feb	2020-02-11
Using a Barycenter compact model for a circuit network Grant 10,366,195 - Ho July 30, 2	2019-07-30
Partitioning electronic circuits for simulation on multiple processors Grant 10,140,396 - Ho Nov	2018-11-27
Validating integrated circuit simulation results Grant 10,068,043 - Ho September 4, 2	2018-09-04
Hierarchical visualization-based analysis of integrated circuits Grant 9,984,195 - Ho May 29, 2	2018-05-29
Solving a circuit network in multicore or distributed computing environment Grant 9,471,733 - Ho October 18, 2	2016-10-18
Validating integrated circuit simulation results Grant 9,454,637 - Ho September 27, 2	2016-09-27
Hierarchical visualization-based analysis of integrated circuits Grant 9,286,430 - Ho March 15, 2	2016-03-15
Using a Barycenter Compact Model for a Circuit Network App 20160048625 - Ho; William Wai Yan	2016-02-18
Partitioning electronic circuits for simulation on multicore processors Grant 9,218,441 - Ho December 22, 2	2015-12-22
Solving a circuit network in hierarchical, multicore, and distributed computing environment Grant 9,129,079 - Ho September 8, 2	2015-09-08
Validating integrated circuit simulation results Grant 9,122,837 - Ho September 1, 2	2015-09-01
Solving a hierarchical circuit network using a barycenter compact model Grant 9,111,058 - Ho August 18, 2	2015-08-18
Partitioning electronic circuits for simulation on multicore processors Grant 8,903,686 - Ho December 2, 2	2014-12-02
Network tearing for circuit simulation Grant 8,818,786 - Ho August 26, 2	2014-08-26
Solving a circuit network in hierarchical, multicore, and distributed computing environment Grant 8,738,335 - Ho May 27, 2	2014-05-27
Validating integrated circuit simulation results Grant 8,719,760 - Ho May 6, 2	2014-05-06
Solving a hierarchical circuit network using a Barycenter compact model Grant 8,694,302 - Ho April 8, 2	2014-04-08
Hierarchical visualization-based analysis of integrated circuits Grant 8,667,455 - Ho March 4, 2	2014-03-04
Network tearing for circuit simulation Grant 8,554,532 - Ho October 8, 2	2013-10-08
Modeling and simulating the impact of imperfectly patterned via arrays on integrated circuits Grant 8,468,482 - Pack , et al. June 18, 2	2013-06-18
Hierarchical variation analysis of integrated circuits Grant 8,453,102 - Pack , et al. May 28, 2	2013-05-28
Using multiple processors to simulate electronic circuits Grant 8,396,696 - Ho March 12, 2	2013-03-12
Validating circuit simulation results Grant 8,166,425 - Ho April 24, 2	2012-04-24
Simulating circuits using network tearing Grant 8,112,264 - Ho February 7, 2	2012-02-07
Simulating circuits by distributed computing Grant 7,827,016 - Ho November 2, 2	2010-11-02
Validating very large network simulation results Grant 7,461,360 - Ho December 2, 2	2008-12-02
Connectivity-based approach for extracting layout parasitics Grant 6,438,729 - Ho August 20, 2	2002-08-20
Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach Grant 6,421,814 - Ho July 16, 2	2002-07-16
Layer-based rule checking for an integrated circuit layout Grant 6,378,110 - Ho April 23, 2	2002-04-23
Connectivity-based approach for extracting layout parasitics Grant 5,999,726 - Ho December 7, 1	1999-12-07
Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach Grant 5,903,469 - Ho May 11, 1	1999-05-11
Connectivity-based approach for extracting parasitic layout in an integrated circuit Grant 5,828,580 - Ho October 27, 1	1998-10-27

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