loadpatents
name:-0.015130996704102
name:-0.023629188537598
name:-0.021836042404175
Ho; Michael V. Patent Filings

Ho; Michael V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ho; Michael V..The latest application filed is for "delay-locked loop clock sharing".

Company Profile
21.23.18
  • Ho; Michael V. - Allen TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Delay-locked loop clock sharing
Grant 11,217,298 - Oh , et al. January 4, 2
2022-01-04
Semiconductor devices having electrostatic discharge layouts for reduced capacitance
Grant 11,158,570 - Ho , et al. October 26, 2
2021-10-26
Apparatuses and methods to perform duty cycle adjustment with back-bias voltage
Grant 11,145,354 - Ho , et al. October 12, 2
2021-10-12
Delay-locked Loop Clock Sharing
App 20210287731 - Oh; Younghoon ;   et al.
2021-09-16
Apparatuses And Methods To Perform Duty Cycle Adjustment With Back-bias Voltage
App 20210201979 - Ho; Michael V. ;   et al.
2021-07-01
Apparatuses and methods to perform duty cycle adjustment with back-bias voltage
Grant 10,950,291 - Ho , et al. March 16, 2
2021-03-16
Systems and methods for improving output signal quality in memory devices
Grant 10,825,506 - Ho November 3, 2
2020-11-03
Memory with a reduced array data bus footprint
Grant 10,790,012 - Ho , et al. September 29, 2
2020-09-29
Semiconductor device with pseudo flow through scheme for power savings
Grant 10,747,470 - Ho , et al. A
2020-08-18
Semiconductor device with a time multiplexing mechanism for size efficiency
Grant 10,747,693 - Ho , et al. A
2020-08-18
Mitigating line-to-line capacitive coupling in a memory die
Grant 10,699,774 - Ho , et al.
2020-06-30
Low power method and system for signal slew rate control
Grant 10,614,870 - Ho , et al.
2020-04-07
Systems and methods for generating stagger delays in memory devices
Grant 10,580,478 - Ho
2020-03-03
Systems And Methods For Generating Stagger Delays In Memory Devices
App 20200035290 - Ho; Michael V.
2020-01-30
Apparatuses And Methods For Pin Capacitance Reduction Including Bond Pads And Circuits In A Semiconductor Device
App 20190363060 - Ho; Michael V. ;   et al.
2019-11-28
Semiconductor Device With Pseudo Flow Through Scheme For Power Savings
App 20190347042 - Ho; Michael V. ;   et al.
2019-11-14
Low Power Method And System For Signal Slew Rate Control
App 20190348104 - Ho; Michael V. ;   et al.
2019-11-14
Memory With A Reduced Array Data Bus Footprint
App 20190348106 - Ho; Michael V. ;   et al.
2019-11-14
Semiconductor Devices Having Electrostatic Discharge Layouts For Reduced Capacitance
App 20190348363 - Ho; Michael V. ;   et al.
2019-11-14
Semiconductor Device With A Time Multiplexing Mechanism For Size Efficiency
App 20190347223 - Ho; Michael V. ;   et al.
2019-11-14
Memory Devices Having A Reduced Global Data Path Footprint And Associated Systems And Methods
App 20190347219 - Ho; Michael V.
2019-11-14
Systems and methods for generating stagger delays in memory devices
Grant 10,460,791 - Ho Oc
2019-10-29
Systems and methods for conserving power in signal quality operations for memory devices
Grant 10,438,649 - Ho O
2019-10-08
Systems and methods for reducing coupling noise between propagation lines for die size efficiency
Grant 10,403,353 - Ho , et al. Sep
2019-09-03
Memory device with a latching mechanism
Grant 10,395,701 - Ho , et al. A
2019-08-27
Systems And Methods For Generating Stagger Delays In Memory Devices
App 20190259440 - Ho; Michael V.
2019-08-22
Systems And Methods For Improving Output Signal Quality In Memory Devices
App 20190259445 - Ho; Michael V.
2019-08-22
Systems And Methods For Conserving Power In Signal Quality Operations For Memory Devices
App 20190259441 - Ho; Michael V.
2019-08-22
Memory with a reduced array data bus footprint
Grant 10,366,743 - Ho , et al. July 30, 2
2019-07-30
Mitigating Line-to-line Capacitive Coupling In A Memory Die
App 20190108869 - Ho; Michael V. ;   et al.
2019-04-11
Mitigating line-to-line capacitive coupling in a memory die
Grant 10,157,661 - Ho , et al. Dec
2018-12-18
Input buffer protection
Grant 8,705,218 - Ho April 22, 2
2014-04-22
Apparatus and method for external to internal clock generation
Grant 8,508,278 - Ho , et al. August 13, 2
2013-08-13
Input Buffer Protection
App 20120215943 - Ho; Michael V.
2012-08-23
Circuit and methods to protect input buffer
Grant 8,169,759 - Ho May 1, 2
2012-05-01
Apparatus And Method For External To Internal Clock Generation
App 20110204949 - Ho; Michael V. ;   et al.
2011-08-25
Apparatus and method for external to internal clock generation
Grant 7,936,199 - Ho , et al. May 3, 2
2011-05-03
Apparatus And Method For External To Internal Clock Generation
App 20090195287 - Ho; Michael V. ;   et al.
2009-08-06
Circuit And Methods To Protect Input Buffer
App 20090191836 - Ho; Michael V.
2009-07-30

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed