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Patent applications and USPTO patent grants for Ho; Jonathan J..The latest application filed is for "methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist".
Patent | Date |
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Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist Grant 7,765,498 - Ho , et al. July 27, 2 | 2010-07-27 |
Method of generating an IC mask using a reduced database Grant 6,868,537 - Ho , et al. March 15, 2 | 2005-03-15 |
Methods and structures for protecting reticles from electrostatic damage Grant 6,569,584 - Ho , et al. May 27, 2 | 2003-05-27 |
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