Ho; Chia-Ming

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ho; Chia-Ming.The latest application filed is for "method of generating modified layout and system therefor".

Company Profile

0.18.15

Ho; Chia-Ming - Hsinchu TW
HO; Chia-Ming - Hsinchu City TW
Ho; Chia-Ming - Hsin-Chu TW
Ho; Chia-Ming - Banciao TW
Ho; Chia-Ming - Banciao City TW
Ho; Chia-Ming - Tao-Yuan TW
Ho; Chia-Ming - Nan Tou Hsien TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method, device and computer program product for integrated circuit layout generation Grant 10,140,407 - Ho , et al. Nov	2018-11-27
Method of generating modified layout and system therefor Grant 10,019,548 - Ho , et al. July 10, 2	2018-07-10
Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout Grant 9,922,162 - Ho , et al. March 20, 2	2018-03-20
Method Of Generating Modified Layout And System Therefor App 20170316142 - HO; Chia-Ming ; et al.	2017-11-02
Method of generating modified layout for RC extraction Grant 9,710,588 - Ho , et al. July 18, 2	2017-07-18
Method, Device And Computer Program Product For Integrated Circuit Layout Generation App 20160147928 - HO; Chia-Ming ; et al.	2016-05-26
Resistive Capacitance Determination Method For Multiple-patterning-multiple Spacer Integrated Circuit Layout App 20160103948 - HO; Chia-Ming ; et al.	2016-04-14
Method Of Generating Modified Layout For Rc Extraction App 20160042108 - HO; Chia-Ming ; et al.	2016-02-11
Method of generating a simulation model of a predefined fabrication process Grant 9,230,052 - Ho , et al. January 5, 2	2016-01-05
Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout Grant 9,218,448 - Ho , et al. December 22, 2	2015-12-22
Resistive Capacitance Determination Method For Multiple-patterning-multiple Spacer Integrated Circuit Layout App 20150205905 - HO; Chia-Ming ; et al.	2015-07-23
Method Of Generating A Simulation Model Of A Predefined Fabrication Process App 20150052493 - HO; Chia-Ming ; et al.	2015-02-19
Multi-patterning mask decomposition method and system Grant 8,954,900 - Ho , et al. February 10, 2	2015-02-10
Multi-patterning Mask Decomposition Method And System App 20150040077 - HO; Chia-Ming ; et al.	2015-02-05
RC extraction for multiple patterning layout design Grant 8,904,314 - Ho , et al. December 2, 2	2014-12-02
Flexible pattern-oriented 3D profile for advanced process nodes Grant 8,887,116 - Ho , et al. November 11, 2	2014-11-11
Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process Grant 8,887,106 - Ho , et al. November 11, 2	2014-11-11
Flexible Pattern-oriented 3d Profile For Advanced Process Nodes App 20140282341 - Ho; Chia-Ming ; et al.	2014-09-18
Parasitic Capacitance Extraction for FinFETs App 20140258962 - Ho; Chia-Ming ; et al.	2014-09-11
Parasitic capacitance extraction for FinFETs Grant 8,826,213 - Ho , et al. September 2, 2	2014-09-02
Accurate parasitic capacitance extraction for ultra large scale integrated circuits Grant 8,572,537 - Su , et al. October 29, 2	2013-10-29
Method Of Generating A Bias-adjusted Layout Design Of A Conductive Feature And Method Of Generating A Simulation Model Of A Predefined Fabrication Process App 20130174112 - HO; Chia-Ming ; et al.	2013-07-04
Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits App 20120260225 - Su; Ke-Ying ; et al.	2012-10-11
Accurate parasitic capacitance extraction for ultra large scale integrated circuits Grant 8,214,784 - Su , et al. July 3, 2	2012-07-03
Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits App 20110023003 - Su; Ke-Ying ; et al.	2011-01-27
Accurate parasitic capacitance extraction for ultra large scale integrated circuits Grant 7,818,698 - Su , et al. October 19, 2	2010-10-19
Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits App 20090007035 - Su; Ke-Ying ; et al.	2009-01-01
Method on scan chain reordering for lowering VLSI power consumption Grant 7,181,664 - Lee , et al. February 20, 2	2007-02-20
Method on scan chain reordering for lowering VLSI power consumption App 20050235182 - Lee, Herng-Jer ; et al.	2005-10-20
Photo-frame style photo album Grant 6,845,582 - Ho , et al. January 25, 2	2005-01-25

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