Ho; Chaw Sing

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ho; Chaw Sing.The latest application filed is for "method of additive manufacturing of object using object material, object manufactured using the same, and method of scanning an object identifier formed using the same".

Company Profile

2.20.15

Ho; Chaw Sing - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method Of Additive Manufacturing Of Object Using Object Material, Object Manufactured Using The Same, And Method Of Scanning An Object Identifier Formed Using The Same App 20210394446 - Tran; Tuan Anh ; et al.	2021-12-23
Electrically-functional optical target Grant 10,336,069 - Ge , et al.	2019-07-02
Fluid ejection devices comprising memory cells Grant 10,319,728 - Ho , et al.	2019-06-11
Electrically-functional Optical Target App 20180222188 - Ge; Ning ; et al.	2018-08-09
Ink property sensing on a printhead Grant 9,908,332 - Ge , et al. March 6, 2	2018-03-06
Printheads With Eprom Cells Having Etched Multi-metal Floating Gates App 20180022103 - GE; Ning ; et al.	2018-01-25
Fluid Ejection Devices Comprising Memory Cells App 20170092653 - Ho; Chaw Sing ; et al.	2017-03-30
Memory cell that prevents charge loss Grant 9,559,106 - Ho , et al. January 31, 2	2017-01-31
Ink Property Sensing On A Printhead App 20160339696 - GE; Ning ; et al.	2016-11-24
V-shape Resistive Memory Element App 20160315256 - Ge; Ning ; et al.	2016-10-27
Fluid ejection apparatuses including a substrate with a bulk layer and a epitaxial layer Grant 9,457,571 - Ge , et al. October 4, 2	2016-10-04
Fluid Ejection Apparatuses Including a Substrate with a Bulk Layer and a Epitaxial Layer App 20160129690 - GE; Ning ; et al.	2016-05-12
Device including active floating gate region area that is smaller than channel area Grant 9,252,149 - Ge , et al. February 2, 2	2016-02-02
Apparatuses including a plate having a recess and a corresponding protrusion to define a chamber Grant 9,199,460 - Ge , et al. December 1, 2	2015-12-01
Memory Cell That Prevents Charge Loss App 20150123186 - Ho; Chaw-Sing ; et al.	2015-05-07
Apparatuses Including A Plate Having A Recess And A Corresponding Protrusion To Define A Chamber App 20150001321 - Ge; Ning ; et al.	2015-01-01
Device Including Active Floating Gate Region Area That Is Smaller Than Channel Area App 20140374812 - Ge; Ning ; et al.	2014-12-25
Modular & Scalable Intra-metal Capacitors App 20100038752 - NG; Chit Hwei ; et al.	2010-02-18
Structure and process for a capacitor and other devices Grant 6,902,981 - Ng , et al. June 7, 2	2005-06-07
Mim And Metal Resistor Formation At Cu Beol Using Only One Extra Mask App 20040087098 - Ng, Chit Hwei ; et al.	2004-05-06
MIM and metal resistor formation at CU beol using only one extra mask Grant 6,730,573 - Ng , et al. May 4, 2	2004-05-04
Structure and process for a capacitor and other devices App 20040072406 - Ng, Chit Hwei ; et al.	2004-04-15
Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology Grant 6,709,918 - Ng , et al. March 23, 2	2004-03-23
Method to fabricate MIM capacitor using damascene process Grant 6,645,810 - Ng , et al. November 11, 2	2003-11-11
Self-integrated vertical MIM capacitor in the dual damascene process Grant 6,624,040 - Ng , et al. September 23, 2	2003-09-23
Method to fabricate NIM capacitor using damascene process App 20030092259 - Ng, Chit Hwei ; et al.	2003-05-15
Method to fabricate MIM capacitor with a curvillnear surface using damascene process Grant 6,548,367 - Ng , et al. April 15, 2	2003-04-15
Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions Grant 6,410,429 - Ho , et al. June 25, 2	2002-06-25
Method to fabricate dual-metal CMOS transistors for sub-0.1 .mu.m ULSI integration Grant 6,410,376 - Ng , et al. June 25, 2	2002-06-25
Method to form uniform silicide features Grant 6,281,117 - Chan , et al. August 28, 2	2001-08-28
Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process Grant 6,180,501 - Pey , et al. January 30, 2	2001-01-30
Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices Grant 6,156,654 - Ho , et al. December 5, 2	2000-12-05
Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices Grant 6,010,954 - Ho , et al. January 4, 2	2000-01-04

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