Hironaga; Nobuo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hironaga; Nobuo.The latest application filed is for "three-dimensional memory device containing annular etch-stop spacer and method of making thereof".

Company Profile

1.5.6

Hironaga; Nobuo - Yokkaichi JP
Hironaga; Nobuo - Yamagata JP
Hironaga; Nobuo - Tokyo JP
Hironaga; Nobuo - Kanagawa JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Three-dimensional memory device containing annular etch-stop spacer and method of making thereof Grant 10,242,994 - Inomata , et al.	2019-03-26
Three-dimensional Memory Device Containing Annular Etch-stop Spacer And Method Of Making Thereof App 20180006049 - INOMATA; Takashi ; et al.	2018-01-04
Set of stepped surfaces formation for a multilevel interconnect structure Grant 9,502,429 - Hironaga November 22, 2	2016-11-22
Set Of Stepped Surfaces Formation For A Multilevel Interconnect Structure App 20160148946 - HIRONAGA; Nobuo	2016-05-26
Semiconductor device manufacturing method, wafer treatment system, and recording medium Grant 8,349,087 - Nambu , et al. January 8, 2	2013-01-08
Semiconductor device manufacturing method, wafer treatment system, and recording medium App 20100184296 - Nambu; Hidetaka ; et al.	2010-07-22
Semiconductor device and manufacturing method for the same Grant 7,229,921 - Hironaga , et al. June 12, 2	2007-06-12
Semiconductor device fabricating method and treating liquid Grant 6,890,864 - Aoki , et al. May 10, 2	2005-05-10
Semiconductor device and manufacturing method for the same App 20030173671 - Hironaga, Nobuo ; et al.	2003-09-18
Semiconductor device fabricating method and treating liquid App 20030134507 - Aoki, Hidemitsu ; et al.	2003-07-17
Semiconductor device fabricating method and treating liquid App 20030027418 - Aoki, Hidemitsu ; et al.	2003-02-06

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