Hirata; Masayoshi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hirata; Masayoshi.The latest application filed is for "interface circuit with damping resistor circuit".

Company Profile

0.10.5

Hirata; Masayoshi - Kanagawa N/A JP
HIRATA, MASAYOSHI - TOKYO JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiring Grant 8,363,421 - Tsukuda , et al. January 29, 2	2013-01-29
Semiconductor device including wiring excellent in impedance matching, and method for designing the same Grant 8,089,004 - Tsukuda , et al. January 3, 2	2012-01-03
Interface Circuit With Damping Resistor Circuit App 20110221488 - Sasaki; Hideki ; et al.	2011-09-15
Semiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiring App 20090244869 - Tsukuda; Tatsuaki ; et al.	2009-10-01
Semiconductor device including wiring excellent in impedance matching, and method for designing the same App 20090084592 - Tsukuda; Tatsuaki ; et al.	2009-04-02
Boosting Circuit With High Voltage Generated At High Speed App 20020153939 - HIRATA, MASAYOSHI	2002-10-24
Semiconductor device with connection terminals in the form of a grid array Grant 6,459,161 - Hirata , et al. October 1, 2	2002-10-01
Semiconductor Device With Connection Terminals In The Form Of A Grid Array App 20020105096 - HIRATA, MASAYOSHI ; et al.	2002-08-08
Erasing device and method of erasure for a storage unit, and storage medium storing program for erasing storage unit Grant 6,118,704 - Hirata September 12, 2	2000-09-12
Non-volatile semiconductor memory device with variable source voltage Grant 5,892,715 - Hirata , et al. April 6, 1	1999-04-06
Data latching circuit for read-out operations of data from memory device Grant 5,841,719 - Hirata November 24, 1	1998-11-24
Non-volatile storage device Grant 5,784,316 - Hirata July 21, 1	1998-07-21
Semiconductor memory and method for substituting a redundancy memory cell Grant 5,684,740 - Hirata November 4, 1	1997-11-04
Non-volatile semiconductor memory device selectively skipping memory cells in programming Grant 5,287,326 - Hirata February 15, 1	1994-02-15

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.